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[AArch64] Make the use of FP instructions optional, but enabled by default.

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This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amara Emerson
2013-10-31 09:32:11 +00:00
parent 0f5e68e3dc
commit c2884320fe
24 changed files with 223 additions and 38 deletions
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59
test/CodeGen/AArch64/variadic.ll
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@@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 < %s | FileCheck --check-prefix=CHECK-NOFP %s
%va_list = type {i8*, i8*, i8*, i32, i32}
@@ -15,11 +16,20 @@ define void @test_simple(i32 %n, ...) {
; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
; CHECK: str x7, [x[[GPRBASE]], #48]
; CHECK-NOFP: sub sp, sp, #[[STACKSIZE:[0-9]+]]
; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
; CHECK-NOFP: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
; CHECK-NOFP: str x7, [x[[GPRBASE]], #48]
; CHECK-NOFP-NOT: str q7,
; CHECK-NOFP: str x1, [sp, #[[GPRFROMSP]]]
; Omit the middle ones
; CHECK: str q0, [sp]
; CHECK: str x1, [sp, #[[GPRFROMSP]]]
; CHECK-NOFP-NOT: str q0, [sp]
%addr = bitcast %va_list* @var to i8*
call void @llvm.va_start(i8* %addr)
; CHECK: movn [[VR_OFFS:w[0-9]+]], #127
@@ -33,6 +43,14 @@ define void @test_simple(i32 %n, ...) {
; CHECK: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
; CHECK-NOFP: str wzr, [x[[VA_LIST]], #28]
; CHECK-NOFP: movn [[GR_OFFS:w[0-9]+]], #55
; CHECK-NOFP: str [[GR_OFFS]], [x[[VA_LIST]], #24]
; CHECK-NOFP: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #56
; CHECK-NOFP: str [[GR_TOP]], [x[[VA_LIST]], #8]
; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
ret void
}
@@ -44,11 +62,19 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
; CHECK: str x7, [x[[GPRBASE]], #32]
; CHECK-NOFP: sub sp, sp, #[[STACKSIZE:[0-9]+]]
; CHECK-NOFP-NOT: str q7,
; CHECK-NOFP: mov x[[GPRBASE:[0-9]+]], sp
; CHECK-NOFP: str x7, [x[[GPRBASE]], #24]
; Omit the middle ones
; CHECK: str q1, [sp]
; CHECK: str x3, [sp, #[[GPRFROMSP]]]
; CHECK-NOFP-NOT: str q1, [sp]
; CHECK-NOFP: str x4, [sp]
%addr = bitcast %va_list* @var to i8*
call void @llvm.va_start(i8* %addr)
; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
@@ -63,6 +89,15 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
; CHECK: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
; CHECK-NOFP: str wzr, [x[[VA_LIST]], #28]
; CHECK-NOFP: movn [[GR_OFFS:w[0-9]+]], #31
; CHECK-NOFP: str [[GR_OFFS]], [x[[VA_LIST]], #24]
; CHECK-NOFP: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #32
; CHECK-NOFP: str [[GR_TOP]], [x[[VA_LIST]], #8]
; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
ret void
}
@@ -75,6 +110,9 @@ define void @test_nospare([8 x i64], [8 x float], ...) {
; CHECK: mov [[STACK:x[0-9]+]], sp
; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
; CHECK-NOFP-NOT: sub sp, sp
; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #64
; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
ret void
}
@@ -87,6 +125,10 @@ define void @test_offsetstack([10 x i64], [3 x float], ...) {
; CHECK: str q7, [x[[FPRBASE]], #64]
; CHECK-NOT: str x{{[0-9]+}},
; CHECK-NOFP-NOT: str q7,
; CHECK-NOT: str x7,
; Omit the middle ones
; CHECK: str q3, [sp]
@@ -102,6 +144,11 @@ define void @test_offsetstack([10 x i64], [3 x float], ...) {
; CHECK: add [[STACK:x[0-9]+]], sp, #96
; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #40
; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
; CHECK-NOFP: str wzr, [x[[VA_LIST]], #28]
; CHECK-NOFP: str wzr, [x[[VA_LIST]], #24]
ret void
}
@@ -110,12 +157,14 @@ declare void @llvm.va_end(i8*)
define void @test_va_end() nounwind {
; CHECK-LABEL: test_va_end:
; CHECK-NEXT: BB#0
; CHECK-NOFP: BB#0
%addr = bitcast %va_list* @var to i8*
call void @llvm.va_end(i8* %addr)
ret void
; CHECK-NEXT: ret
; CHECK-NOFP-NEXT: ret
}
declare void @llvm.va_copy(i8* %dest, i8* %src)
@@ -132,6 +181,8 @@ define void @test_va_copy() {
; CHECK: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var]
; CHECK: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
; CHECK-NOFP: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var]
; CHECK-NOFP: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list]
@@ -140,6 +191,14 @@ define void @test_va_copy() {
; CHECK: str [[BLOCK]], [x[[DEST_LIST]], #24]
; CHECK-NOFP: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list]
; CHECK-NOFP: ldr [[BLOCK:x[0-9]+]], [x[[SRC_LIST]], #24]
; CHECK-NOFP: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list
; CHECK-NOFP: str [[BLOCK]], [x[[DEST_LIST]], #24]
ret void
; CHECK: ret
; CHECK-NOFP: ret
}