6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

This assert is overly restrictive and does not work for mips16.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2012-12-20 05:09:15 +00:00
parent 1f23239c5b
commit c28ee9622a
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -1048,7 +1048,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
static unsigned static unsigned
AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
{ {
assert(RC->contains(PReg) && "Not the correct regclass!");
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
MF.getRegInfo().addLiveIn(PReg, VReg); MF.getRegInfo().addLiveIn(PReg, VReg);
return VReg; return VReg;