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Handle abnormal jmpl syntax correctly

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2001-10-15 19:21:31 +00:00
parent 7b851abd85
commit c28f6d6258
1 changed files with 50 additions and 35 deletions
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85
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
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@ -46,10 +46,8 @@ private :
//void processMethodArgument(const MethodArgument *MA);
void emitBasicBlock(const BasicBlock *BB);
void emitMachineInst(const MachineInstr *MI);
void printOperand(const MachineOperand &Op);
//void writeOperand(const Value *Op, bool PrintType, bool PrintName = true);
// enterSection - Use this method to enter a different section of the output
// executable. This is used to only output neccesary section transitions.
@ -120,6 +118,41 @@ private :
};
void SparcAsmPrinter::printOperand(const MachineOperand &Op) {
switch (Op.getOperandType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
case MachineOperand::MO_MachineRegister: {
int RegNum = (int)Op.getAllocatedRegNum();
// ****this code is temporary till NULL Values are fixed
if (RegNum == 10000) {
Out << "<NULL VALUE>";
} else {
Out << "%" << Target.getRegInfo().getUnifiedRegName(RegNum);
}
break;
}
case MachineOperand::MO_PCRelativeDisp: {
const Value *Val = Op.getVRegValue();
if (!Val) {
Out << "\t<*NULL Value*>";
} else if (const BasicBlock *BB = dyn_cast<const BasicBlock>(Val)) {
Out << getID(BB);
} else {
Out << "<unknown value=" << Val << ">";
}
break;
}
default:
Out << Op; // use dump field
break;
}
}
void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
unsigned Opcode = MI->getOpCode();
@ -128,6 +161,19 @@ void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
Out << "\t" << TargetInstrDescriptors[Opcode].opCodeString << "\t";
switch (Opcode) { // Some opcodes have special syntax...
case JMPL:
assert(MI->getNumOperands() == 3 && "Unexpected JMPL instr!");
printOperand(MI->getOperand(0));
Out << "+";
printOperand(MI->getOperand(0));
Out << ", ";
printOperand(MI->getOperand(0));
Out << endl;
return;
default: break;
}
unsigned Mask = getOperandMask(Opcode);
bool NeedComma = false;
@ -138,38 +184,7 @@ void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
if (NeedComma) Out << ", "; // Handle comma outputing
NeedComma = true;
switch (Op.getOperandType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
case MachineOperand::MO_MachineRegister: {
int RegNum = (int)Op.getAllocatedRegNum();
// ****this code is temporary till NULL Values are fixed
if (RegNum == 10000) {
Out << "<NULL VALUE>";
continue;
}
Out << "%" << Target.getRegInfo().getUnifiedRegName(RegNum);
break;
}
case MachineOperand::MO_PCRelativeDisp: {
const Value *Val = Op.getVRegValue();
if (!Val) {
Out << "\t<*NULL Value*>";
} else if (const BasicBlock *BB = dyn_cast<const BasicBlock>(Val)) {
Out << getID(BB);
} else {
Out << "<unknown value=" << Val << ">";
}
break;
}
default:
Out << Op; // use dump field
break;
}
printOperand(Op);
}
Out << endl;
}