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Add fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136375 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2862,6 +2862,10 @@ defm BIC : AsI1_bin_irs<0b1110, "bic",
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IIC_iBITi, IIC_iBITr, IIC_iBITsr,
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BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
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// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
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// like in the actual instruction encoding. The complexity of mapping the mask
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// to the lsb/msb pair should be handled by ISel, not encapsulated in the
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// instruction description.
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def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
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AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
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"bfc", "\t$Rd, $imm", "$src = $Rd",
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@ -2873,7 +2877,7 @@ def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
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let Inst{6-0} = 0b0011111;
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let Inst{15-12} = Rd;
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let Inst{11-7} = imm{4-0}; // lsb
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let Inst{20-16} = imm{9-5}; // width
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let Inst{20-16} = imm{9-5}; // msb
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}
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// A8.6.18 BFI - Bitfield insert (Encoding A1)
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