From c2d98bc0d682419f09659d94afefd6a6266dd6ee Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Sun, 6 Sep 2009 12:41:19 +0000 Subject: [PATCH] Remove some not-really-used variables, as warned about by icc (#593, partial). Patch by Erick Tryzelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocPBQP.cpp | 4 ---- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 2 -- lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 8 ++------ lib/CodeGen/StackSlotColoring.cpp | 2 -- lib/Support/regengine.inc | 15 +++++++++------ lib/System/Unix/Program.inc | 3 --- lib/Target/ARM/Thumb2SizeReduction.cpp | 2 -- lib/Target/PowerPC/PPCISelLowering.cpp | 3 --- lib/Target/X86/AsmPrinter/X86MCInstLower.cpp | 3 +-- lib/Target/X86/X86ISelLowering.cpp | 3 +-- lib/Target/XCore/XCoreRegisterInfo.cpp | 13 ++++++------- lib/Transforms/Scalar/CondPropagate.cpp | 3 --- 12 files changed, 19 insertions(+), 42 deletions(-) diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index 12da38fa21a..b62d4def7e4 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -691,10 +691,6 @@ void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, } bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) { - - static unsigned round = 0; - (void) round; - // Set to true if we have any spills bool anotherRoundNeeded = false; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index a580b93c836..6c6e96abac8 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -243,10 +243,8 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { // Compute the latency for the node. We use the sum of the latencies for // all nodes flagged together into this SUnit. SU->Latency = 0; - bool SawMachineOpcode = false; for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) if (N->isMachineOpcode()) { - SawMachineOpcode = true; SU->Latency += InstrItins. getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass()); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index cd05f7124d2..b0a6a6e17fb 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -1714,11 +1714,9 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, MachineFunction *CurMF = FuncInfo.MF; // Figure out which block is immediately after the current one. - MachineBasicBlock *NextBlock = 0; MachineFunction::iterator BBI = CR.CaseBB; - if (++BBI != FuncInfo.MF->end()) - NextBlock = BBI; + if (++BBI != FuncInfo.MF->end()) {} const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); @@ -1787,11 +1785,9 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, MachineFunction *CurMF = FuncInfo.MF; // Figure out which block is immediately after the current one. - MachineBasicBlock *NextBlock = 0; MachineFunction::iterator BBI = CR.CaseBB; - if (++BBI != FuncInfo.MF->end()) - NextBlock = BBI; + if (++BBI != FuncInfo.MF->end()) {} Case& FrontCase = *CR.Range.first; Case& BackCase = *(CR.Range.second-1); diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp index 5884b8213bb..e62c0506b3e 100644 --- a/lib/CodeGen/StackSlotColoring.cpp +++ b/lib/CodeGen/StackSlotColoring.cpp @@ -558,7 +558,6 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII, SmallVector Uses; while (++MII != MBB->end()) { - bool FoundUse = false; bool FoundKill = false; const TargetInstrDesc &TID = MII->getDesc(); for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) { @@ -581,7 +580,6 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII, const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); if (RC && !RC->contains(NewReg)) return false; - FoundUse = true; if (MO.isKill()) FoundKill = true; diff --git a/lib/Support/regengine.inc b/lib/Support/regengine.inc index ac848bcec88..f1ba56b02b2 100644 --- a/lib/Support/regengine.inc +++ b/lib/Support/regengine.inc @@ -302,7 +302,6 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst) char *ssp; /* start of string matched by subsubRE */ char *sep; /* end of string matched by subsubRE */ char *oldssp; /* previous ssp */ - char *dp; AT("diss", start, stop, startst, stopst); sp = start; @@ -361,7 +360,7 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst) esub = es - 1; /* did innards match? */ if (slow(m, sp, rest, ssub, esub) != NULL) { - dp = dissect(m, sp, rest, ssub, esub); + char *dp = dissect(m, sp, rest, ssub, esub); assert(dp == rest); } else /* no */ assert(sp == rest); @@ -399,8 +398,10 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst) } assert(sep == rest); /* must exhaust substring */ assert(slow(m, ssp, sep, ssub, esub) == rest); - dp = dissect(m, ssp, sep, ssub, esub); - assert(dp == sep); + { + char *dp = dissect(m, ssp, sep, ssub, esub); + assert(dp == sep); + } sp = rest; break; case OCH_: @@ -434,8 +435,10 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst) else assert(OP(m->g->strip[esub]) == O_CH); } - dp = dissect(m, sp, rest, ssub, esub); - assert(dp == rest); + { + char *dp = dissect(m, sp, rest, ssub, esub); + assert(dp == rest); + } sp = rest; break; case O_PLUS: diff --git a/lib/System/Unix/Program.inc b/lib/System/Unix/Program.inc index 84e025cd5d5..adf7390f9fb 100644 --- a/lib/System/Unix/Program.inc +++ b/lib/System/Unix/Program.inc @@ -116,9 +116,7 @@ static bool RedirectIO(const Path *Path, int FD, std::string* ErrMsg) { return false; } -static bool Timeout = false; static void TimeOutHandler(int Sig) { - Timeout = true; } static void SetMemoryLimits (unsigned size) @@ -233,7 +231,6 @@ Program::Wait(unsigned secondsToWait, // Install a timeout handler. if (secondsToWait) { - Timeout = false; Act.sa_sigaction = 0; Act.sa_handler = TimeOutHandler; sigemptyset(&Act.sa_mask); diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp index c95b4c0e85c..0784fbed880 100644 --- a/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -262,7 +262,6 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, bool HasImmOffset = false; bool HasShift = false; bool isLdStMul = false; - bool isPopPush = false; unsigned Opc = Entry.NarrowOpc1; unsigned OpNum = 3; // First 'rest' of operands. switch (Entry.WideOpc) { @@ -301,7 +300,6 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Mode = MI->getOperand(1).getImm(); if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) { Opc = Entry.NarrowOpc2; - isPopPush = true; OpNum = 2; } else if (Entry.WideOpc == ARM::t2LDM_RET || !isARMLowRegister(BaseReg) || diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 69c02ac533e..2a3ca468d78 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2876,7 +2876,6 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, SmallVector MemOpChains; for (unsigned i = 0; i != NumOps; ++i) { - bool inMem = false; SDValue Arg = Outs[i].Val; ISD::ArgFlagsTy Flags = Outs[i].Flags; @@ -2963,7 +2962,6 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, false, MemOpChains, TailCallArguments, dl); - inMem = true; } ArgOffset += PtrByteSize; break; @@ -3003,7 +3001,6 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, false, MemOpChains, TailCallArguments, dl); - inMem = true; } if (isPPC64) ArgOffset += 8; diff --git a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp index e3bbc8d6fe8..019ee296eaa 100644 --- a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp +++ b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp @@ -119,7 +119,6 @@ MCSymbol *X86ATTAsmPrinter::GetJumpTableSymbol(const MachineOperand &MO) { raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex(); - MCSymbol *NegatedSymbol = 0; switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); @@ -129,7 +128,7 @@ MCSymbol *X86ATTAsmPrinter::GetJumpTableSymbol(const MachineOperand &MO) { case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: break; // Subtract the pic base. - NegatedSymbol = GetPICBaseSymbol(); + GetPICBaseSymbol(); break; } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 34e53f02ef3..d2517a2e28e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5198,10 +5198,9 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); EVT VT = Op.getValueType(); EVT EltVT = VT; - unsigned EltNum = 1; if (VT.isVector()) { EltVT = VT.getVectorElementType(); - EltNum = VT.getVectorNumElements(); + VT.getVectorNumElements(); } std::vector CV; if (EltVT == MVT::f64) { diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 8fbcb51eb0d..4c92026d5bc 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -226,7 +226,6 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, bool isUs = isImmUs(Offset); unsigned FramePtr = XCore::R10; - MachineInstr *New = 0; if (!isUs) { if (!RS) { std::string msg; @@ -239,18 +238,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, loadConstant(MBB, II, ScratchReg, Offset, dl); switch (MI.getOpcode()) { case XCore::LDWFI: - New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) + BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) .addReg(FramePtr) .addReg(ScratchReg, RegState::Kill); break; case XCore::STWFI: - New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) + BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) .addReg(Reg, getKillRegState(isKill)) .addReg(FramePtr) .addReg(ScratchReg, RegState::Kill); break; case XCore::LDAWFI: - New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) + BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) .addReg(FramePtr) .addReg(ScratchReg, RegState::Kill); break; @@ -260,18 +259,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } else { switch (MI.getOpcode()) { case XCore::LDWFI: - New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) + BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) .addReg(FramePtr) .addImm(Offset); break; case XCore::STWFI: - New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) + BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) .addReg(Reg, getKillRegState(isKill)) .addReg(FramePtr) .addImm(Offset); break; case XCore::LDAWFI: - New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) + BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) .addReg(FramePtr) .addImm(Offset); break; diff --git a/lib/Transforms/Scalar/CondPropagate.cpp b/lib/Transforms/Scalar/CondPropagate.cpp index 09fc050e13c..5b573f492cd 100644 --- a/lib/Transforms/Scalar/CondPropagate.cpp +++ b/lib/Transforms/Scalar/CondPropagate.cpp @@ -191,8 +191,6 @@ void CondProp::SimplifyPredecessors(SwitchInst *SI) { if (&*BBI != SI) return; - bool RemovedPreds = false; - // Ok, we have this really simple case, walk the PHI operands, looking for // constants. Walk from the end to remove operands from the end when // possible, and to avoid invalidating "i". @@ -204,7 +202,6 @@ void CondProp::SimplifyPredecessors(SwitchInst *SI) { RevectorBlockTo(PN->getIncomingBlock(i-1), SI->getSuccessor(DestCase)); ++NumSwThread; - RemovedPreds = true; // If there were two predecessors before this simplification, or if the // PHI node contained all the same value except for the one we just