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https://github.com/c64scene-ar/llvm-6502.git
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[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
a3e8e06be7
commit
c2e835fd7e
@ -42,56 +42,56 @@ def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, IIBranch, MIPS_BRANCH_F>,
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def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, IIBranch, MIPS_BRANCH_T>,
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BC1F_FM_MM<0x1d>;
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def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
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ROUND_W_FM_MM<0, 0x6c>;
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def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
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ROUND_W_FM_MM<0, 0x24>;
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def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
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ROUND_W_FM_MM<0, 0x2c>;
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def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
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ROUND_W_FM_MM<0, 0xec>;
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def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
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ROUND_W_FM_MM<0, 0xac>;
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def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,IIFsqrtSingle,
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fsqrt>, ROUND_W_FM_MM<0, 0x28>;
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def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
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ROUND_W_FM_MM<1, 0x6c>;
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def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ROUND_W_FM_MM<1, 0x24>;
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def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
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ROUND_W_FM_MM<1, 0x2c>;
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def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
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ROUND_W_FM_MM<1, 0xec>;
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def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
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ROUND_W_FM_MM<1, 0xac>;
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def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
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IIFsqrtDouble, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
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def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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ROUND_W_FM_MM<0, 0x4>;
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def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ROUND_W_FM_MM<1, 0x4>;
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def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>,
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def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
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ABS_FM_MM<0, 0xd>;
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def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>,
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ABS_FM_MM<0, 0x1>;
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def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>,
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def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
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ABS_FM_MM<0, 0x2d>;
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def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABS_FM_MM<0, 0x4d>;
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def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABS_FM_MM<1, 0x4d>;
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def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABS_FM_MM<0, 0x6d>;
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def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
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ABS_FM_MM<1, 0x6d>;
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def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, IIFcvt, fabs>,
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def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
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ABS_FM_MM<1, 0xd>;
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def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, IIFcvt, fneg>,
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def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
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ABS_FM_MM<1, 0x2d>;
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def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>,
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@ -246,86 +246,86 @@ defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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//===----------------------------------------------------------------------===//
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def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
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ABSS_FM<0xc, 16>;
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def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
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ABSS_FM<0xd, 16>;
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def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
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ABSS_FM<0xe, 16>;
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def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
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ABSS_FM<0xf, 16>;
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def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x24, 16>;
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defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
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defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
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defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
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defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>;
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defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>;
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defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
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ABSS_FM<0x8, 16>;
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
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ABSS_FM<0x8, 17>;
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def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
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ABSS_FM<0x9, 16>;
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def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
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ABSS_FM<0x9, 17>;
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def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
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ABSS_FM<0xa, 16>;
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def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
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ABSS_FM<0xa, 17>;
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def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
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ABSS_FM<0xb, 16>;
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def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
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ABSS_FM<0xb, 17>;
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}
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def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>,
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def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x20, 20>;
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def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x25, 16>;
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def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x25, 17>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 20>;
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def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 16>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>,
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>,
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 21>;
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def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 20>;
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def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
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def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 16>;
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def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>,
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def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x21, 21>;
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}
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let isPseudo = 1, isCodeGenOnly = 1 in {
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def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>;
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def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>;
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def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
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def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>;
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def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
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def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
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def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
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def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
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def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
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def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
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}
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let Predicates = [NoNaNsFPMath, HasStdEnc] in {
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def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>,
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def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
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ABSS_FM<0x5, 16>;
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def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>,
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def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
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ABSS_FM<0x7, 16>;
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defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
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defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
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defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
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defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
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}
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def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle,
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@ -20,7 +20,6 @@ def IIAlu : InstrItinClass;
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def IILoad : InstrItinClass;
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def IIStore : InstrItinClass;
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def IIBranch : InstrItinClass;
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def IIFcvt : InstrItinClass;
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def IIFmove : InstrItinClass;
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def IIFcmp : InstrItinClass;
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def IIFadd : InstrItinClass;
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@ -36,13 +35,16 @@ def IIFStore : InstrItinClass;
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def IIFmoveC1 : InstrItinClass;
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def IIPseudo : InstrItinClass;
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def II_ABS : InstrItinClass;
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def II_ADDI : InstrItinClass;
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def II_ADDIU : InstrItinClass;
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def II_ADDU : InstrItinClass;
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def II_AND : InstrItinClass;
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def II_ANDI : InstrItinClass;
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def II_CEIL : InstrItinClass;
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def II_CLO : InstrItinClass;
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def II_CLZ : InstrItinClass;
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def II_CVT : InstrItinClass;
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def II_DADDIU : InstrItinClass;
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def II_DADDU : InstrItinClass;
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def II_DDIV : InstrItinClass;
|
||||
@ -64,26 +66,29 @@ def II_DSRL : InstrItinClass;
|
||||
def II_DSRL32 : InstrItinClass;
|
||||
def II_DSRLV : InstrItinClass;
|
||||
def II_DSUBU : InstrItinClass;
|
||||
def II_FLOOR : InstrItinClass;
|
||||
def II_LUI : InstrItinClass;
|
||||
def II_MADD : InstrItinClass;
|
||||
def II_MADDU : InstrItinClass;
|
||||
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
|
||||
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
|
||||
def II_MOVF : InstrItinClass;
|
||||
def II_MOVN : InstrItinClass;
|
||||
def II_MOVT : InstrItinClass;
|
||||
def II_MOVZ : InstrItinClass;
|
||||
def II_MSUB : InstrItinClass;
|
||||
def II_MSUBU : InstrItinClass;
|
||||
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
|
||||
def II_MUL : InstrItinClass;
|
||||
def II_MULT : InstrItinClass;
|
||||
def II_MULTU : InstrItinClass;
|
||||
def II_MSUB : InstrItinClass;
|
||||
def II_MSUBU : InstrItinClass;
|
||||
def II_NEG : InstrItinClass;
|
||||
def II_NOR : InstrItinClass;
|
||||
def II_OR : InstrItinClass;
|
||||
def II_ORI : InstrItinClass;
|
||||
def II_RDHWR : InstrItinClass;
|
||||
def II_ROTR : InstrItinClass;
|
||||
def II_ROTRV : InstrItinClass;
|
||||
def II_ROUND : InstrItinClass;
|
||||
def II_SEB : InstrItinClass;
|
||||
def II_SEH : InstrItinClass;
|
||||
def II_SLL : InstrItinClass;
|
||||
@ -95,6 +100,7 @@ def II_SRAV : InstrItinClass;
|
||||
def II_SRL : InstrItinClass;
|
||||
def II_SRLV : InstrItinClass;
|
||||
def II_SUBU : InstrItinClass;
|
||||
def II_TRUNC : InstrItinClass;
|
||||
def II_XOR : InstrItinClass;
|
||||
def II_XORI : InstrItinClass;
|
||||
|
||||
@ -161,7 +167,13 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>,
|
||||
InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>,
|
||||
InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>,
|
||||
InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<IIFcmp , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<IIFadd , [InstrStage<4, [ALU]>]>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user