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Enable PostRA scheduling for SPU.

Browse Source 
This speeds up selected test cases with up to
5% - no slowdowns observed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120286 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-11-29 10:30:25 +00:00
parent b00f24b13c
commit c2ebfd454c
4 changed files with 29 additions and 4 deletions
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21
lib/Target/CellSPU/SPUSubtarget.cpp
View File

@ -14,6 +14,8 @@
#include "SPUSubtarget.h" #include "SPUSubtarget.h"
#include "SPU.h" #include "SPU.h"
#include "SPUGenSubtarget.inc" #include "SPUGenSubtarget.inc"
#include "llvm/ADT/SmallVector.h"
#include "SPURegisterInfo.h"
using namespace llvm; using namespace llvm;
@ -34,3 +36,22 @@ SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &FS) :
/// producing code for the JIT. /// producing code for the JIT.
void SPUSubtarget::SetJITMode() { void SPUSubtarget::SetJITMode() {
} }
/// Enable PostRA scheduling for optimization levels -O2 and -O3.
bool SPUSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
Mode = TargetSubtarget::ANTIDEP_CRITICAL;
// CriticalPathsRCs seems to be the set of
// RegisterClasses that antidep breakings are performed for.
// Do it for all register classes
CriticalPathRCs.clear();
CriticalPathRCs.push_back(&SPU::R8CRegClass);
CriticalPathRCs.push_back(&SPU::R16CRegClass);
CriticalPathRCs.push_back(&SPU::R32CRegClass);
CriticalPathRCs.push_back(&SPU::R32FPRegClass);
CriticalPathRCs.push_back(&SPU::R64CRegClass);
CriticalPathRCs.push_back(&SPU::VECREGRegClass);
return OptLevel >= CodeGenOpt::Default;
}

4
lib/Target/CellSPU/SPUSubtarget.h
View File

@ -84,6 +84,10 @@ namespace llvm {
"-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128" "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128"
"-s:128:128-n32:64"; "-s:128:128-n32:64";
} }
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
}; };
} // End llvm namespace } // End llvm namespace

6
test/CodeGen/CellSPU/sext128.ll
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@ -13,8 +13,8 @@ entry:
; CHECK: long 66051 ; CHECK: long 66051
; CHECK: long 67438087 ; CHECK: long 67438087
; CHECK-NOT: rotqmbyi ; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa ; CHECK: lqa
; CHECK: rotmai
; CHECK: shufb ; CHECK: shufb
} }
@ -27,8 +27,8 @@ entry:
; CHECK: long 269488144 ; CHECK: long 269488144
; CHECK: long 66051 ; CHECK: long 66051
; CHECK-NOT: rotqmbyi ; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa ; CHECK: lqa
; CHECK: rotmai
; CHECK: shufb ; CHECK: shufb
} }
@ -42,8 +42,8 @@ entry:
; CHECK: long 269488144 ; CHECK: long 269488144
; CHECK: long 66051 ; CHECK: long 66051
; CHECK-NOT: rotqmbyi ; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa ; CHECK: lqa
; CHECK: rotmai
; CHECK: shufb ; CHECK: shufb
} }

2
test/CodeGen/CellSPU/shuffles.ll
View File

@ -1,4 +1,4 @@
; RUN: llc --march=cellspu < %s | FileCheck %s ; RUN: llc -O1 --march=cellspu < %s | FileCheck %s
define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) { define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
; CHECK: cwd {{\$.}}, 0($sp) ; CHECK: cwd {{\$.}}, 0($sp)