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Implement atomicrmw operations in 32 and 64 bits for SPARCv9.

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These all use the compare-and-swap CASA/CASXA instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199975 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2014-01-24 06:23:31 +00:00
parent 8c6a26194b
commit c30791627e
4 changed files with 261 additions and 12 deletions
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83
test/CodeGen/SPARC/atomics.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -march=sparcv9 | FileCheck %s
; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: test_atomic_i32
; CHECK: ld [%o0]
@@ -61,3 +61,84 @@ entry:
%b = atomicrmw xchg i32* %ptr, i32 42 monotonic
ret i32 %b
}
; CHECK-LABEL: test_load_add_32
; CHECK: membar
; CHECK: add
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw add i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_sub_64
; CHECK: membar
; CHECK: sub
; CHECK: casx [%o0]
; CHECK: membar
define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
entry:
%0 = atomicrmw sub i64* %p, i64 %v seq_cst
ret i64 %0
}
; CHECK-LABEL: test_load_xor_32
; CHECK: membar
; CHECK: xor
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw xor i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_and_32
; CHECK: membar
; CHECK: and
; CHECK-NOT: xor
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw and i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_nand_32
; CHECK: membar
; CHECK: and
; CHECK: xor
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw nand i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_max_64
; CHECK: membar
; CHECK: cmp
; CHECK: movg %xcc
; CHECK: casx [%o0]
; CHECK: membar
define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
entry:
%0 = atomicrmw max i64* %p, i64 %v seq_cst
ret i64 %0
}
; CHECK-LABEL: test_load_umin_32
; CHECK: membar
; CHECK: cmp
; CHECK: movleu %icc
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw umin i32* %p, i32 %v seq_cst
ret i32 %0
}