6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-14 13:07:31 +00:00
Code Issues Projects Releases Wiki Activity

ignore register zero in isRegTiedToUseOperand, following the example of

Browse Source 
isRegTiedToDefOperand.  Thanks to Bob for pointing this out!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68734 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-04-09 23:33:34 +00:00
parent 3ca15c989c
commit c30aa7b3de
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/MachineInstr.cpp
View File

@ -698,7 +698,7 @@ bool MachineInstr::isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx){
if (getOpcode() == TargetInstrInfo::INLINEASM) {
assert(DefOpIdx >= 2);
const MachineOperand &MO = getOperand(DefOpIdx);
if (!MO.isReg() || !MO.isDef())
if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
return false;
// Determine the actual operand no corresponding to this index.
unsigned DefNo = 0;