mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
Convert DOUT to DEBUG(errs()...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
1e973aae79
commit
c3115a02c5
@ -33,9 +33,8 @@
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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@ -299,15 +298,20 @@ namespace {
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template <typename ItTy>
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void printIntervals(const char* const str, ItTy i, ItTy e) const {
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if (str) DOUT << str << " intervals:\n";
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for (; i != e; ++i) {
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DOUT << "\t" << *i->first << " -> ";
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unsigned reg = i->first->reg;
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if (TargetRegisterInfo::isVirtualRegister(reg)) {
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reg = vrm_->getPhys(reg);
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}
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DOUT << tri_->getName(reg) << '\n';
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}
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DEBUG({
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if (str)
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errs() << str << " intervals:\n";
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for (; i != e; ++i) {
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errs() << "\t" << *i->first << " -> ";
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unsigned reg = i->first->reg;
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if (TargetRegisterInfo::isVirtualRegister(reg))
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reg = vrm_->getPhys(reg);
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errs() << tri_->getName(reg) << '\n';
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}
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});
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}
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};
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char RALinScan::ID = 0;
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@ -384,8 +388,8 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
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// Try to coalesce.
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if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
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DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
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<< '\n';
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DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
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<< '\n');
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vrm_->clearVirt(cur.reg);
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vrm_->assignVirt2Phys(cur.reg, PhysReg);
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@ -482,21 +486,21 @@ void RALinScan::initIntervalSets()
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}
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}
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void RALinScan::linearScan()
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{
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void RALinScan::linearScan() {
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// linear scan algorithm
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DOUT << "********** LINEAR SCAN **********\n";
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DEBUG(errs() << "********** Function: "
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<< mf_->getFunction()->getName() << '\n');
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DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
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DEBUG({
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errs() << "********** LINEAR SCAN **********\n"
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<< "********** Function: "
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<< mf_->getFunction()->getName() << '\n';
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printIntervals("fixed", fixed_.begin(), fixed_.end());
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});
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while (!unhandled_.empty()) {
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// pick the interval with the earliest start point
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LiveInterval* cur = unhandled_.top();
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unhandled_.pop();
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++NumIters;
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DOUT << "\n*** CURRENT ***: " << *cur << '\n';
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DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
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if (!cur->empty()) {
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processActiveIntervals(cur->beginNumber());
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@ -511,15 +515,17 @@ void RALinScan::linearScan()
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// assign it one.
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assignRegOrStackSlotAtInterval(cur);
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DEBUG(printIntervals("active", active_.begin(), active_.end()));
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DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
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DEBUG({
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printIntervals("active", active_.begin(), active_.end());
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printIntervals("inactive", inactive_.begin(), inactive_.end());
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});
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}
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// Expire any remaining active intervals
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while (!active_.empty()) {
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IntervalPtr &IP = active_.back();
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unsigned reg = IP.first->reg;
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DOUT << "\tinterval " << *IP.first << " expired\n";
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DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
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assert(TargetRegisterInfo::isVirtualRegister(reg) &&
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"Can only allocate virtual registers!");
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reg = vrm_->getPhys(reg);
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@ -528,9 +534,11 @@ void RALinScan::linearScan()
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}
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// Expire any remaining inactive intervals
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DEBUG(for (IntervalPtrs::reverse_iterator
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i = inactive_.rbegin(); i != inactive_.rend(); ++i)
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DOUT << "\tinterval " << *i->first << " expired\n");
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DEBUG({
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for (IntervalPtrs::reverse_iterator
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i = inactive_.rbegin(); i != inactive_.rend(); ++i)
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errs() << "\tinterval " << *i->first << " expired\n";
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});
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inactive_.clear();
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// Add live-ins to every BB except for entry. Also perform trivial coalescing.
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@ -565,7 +573,7 @@ void RALinScan::linearScan()
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}
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}
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DOUT << *vrm_;
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DEBUG(errs() << *vrm_);
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// Look for physical registers that end up not being allocated even though
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// register allocator had to spill other registers in its register class.
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@ -579,7 +587,7 @@ void RALinScan::linearScan()
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/// to the inactive list.
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void RALinScan::processActiveIntervals(unsigned CurPoint)
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{
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DOUT << "\tprocessing active intervals:\n";
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DEBUG(errs() << "\tprocessing active intervals:\n");
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for (unsigned i = 0, e = active_.size(); i != e; ++i) {
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LiveInterval *Interval = active_[i].first;
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@ -589,7 +597,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
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IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
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if (IntervalPos == Interval->end()) { // Remove expired intervals.
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DOUT << "\t\tinterval " << *Interval << " expired\n";
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DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
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assert(TargetRegisterInfo::isVirtualRegister(reg) &&
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"Can only allocate virtual registers!");
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reg = vrm_->getPhys(reg);
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@ -602,7 +610,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
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} else if (IntervalPos->start > CurPoint) {
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// Move inactive intervals to inactive list.
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DOUT << "\t\tinterval " << *Interval << " inactive\n";
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DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
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assert(TargetRegisterInfo::isVirtualRegister(reg) &&
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"Can only allocate virtual registers!");
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reg = vrm_->getPhys(reg);
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@ -625,7 +633,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
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/// ones to the active list.
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void RALinScan::processInactiveIntervals(unsigned CurPoint)
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{
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DOUT << "\tprocessing inactive intervals:\n";
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DEBUG(errs() << "\tprocessing inactive intervals:\n");
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for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
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LiveInterval *Interval = inactive_[i].first;
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@ -635,7 +643,7 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint)
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IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
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if (IntervalPos == Interval->end()) { // remove expired intervals.
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DOUT << "\t\tinterval " << *Interval << " expired\n";
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DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
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// Pop off the end of the list.
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inactive_[i] = inactive_.back();
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@ -643,7 +651,7 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint)
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--i; --e;
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} else if (IntervalPos->start <= CurPoint) {
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// move re-activated intervals in active list
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DOUT << "\t\tinterval " << *Interval << " active\n";
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DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
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assert(TargetRegisterInfo::isVirtualRegister(reg) &&
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"Can only allocate virtual registers!");
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reg = vrm_->getPhys(reg);
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@ -769,10 +777,12 @@ void RALinScan::findIntervalsToSpill(LiveInterval *cur,
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float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
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SmallVector<LiveInterval*, 8> SLIs[3];
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DOUT << "\tConsidering " << NumCands << " candidates: ";
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DEBUG(for (unsigned i = 0; i != NumCands; ++i)
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DOUT << tri_->getName(Candidates[i].first) << " ";
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DOUT << "\n";);
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DEBUG({
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errs() << "\tConsidering " << NumCands << " candidates: ";
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for (unsigned i = 0; i != NumCands; ++i)
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errs() << tri_->getName(Candidates[i].first) << " ";
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errs() << "\n";
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});
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// Calculate the number of conflicts of each candidate.
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for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
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@ -877,9 +887,8 @@ namespace {
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/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
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/// spill.
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void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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{
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DOUT << "\tallocating current interval: ";
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void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
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DEBUG(errs() << "\tallocating current interval: ");
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// This is an implicitly defined live interval, just assign any register.
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const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
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@ -887,7 +896,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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unsigned physReg = vrm_->getRegAllocPref(cur->reg);
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if (!physReg)
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physReg = *RC->allocation_order_begin(*mf_);
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DOUT << tri_->getName(physReg) << '\n';
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DEBUG(errs() << tri_->getName(physReg) << '\n');
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// Note the register is not really in use.
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vrm_->assignVirt2Phys(cur->reg, physReg);
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return;
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@ -1020,7 +1029,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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// the free physical register and add this interval to the active
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// list.
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if (physReg) {
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DOUT << tri_->getName(physReg) << '\n';
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DEBUG(errs() << tri_->getName(physReg) << '\n');
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vrm_->assignVirt2Phys(cur->reg, physReg);
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addRegUse(physReg);
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active_.push_back(std::make_pair(cur, cur->begin()));
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@ -1036,7 +1045,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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}
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return;
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}
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DOUT << "no free registers\n";
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DEBUG(errs() << "no free registers\n");
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// Compile the spill weights into an array that is better for scanning.
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std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
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@ -1054,7 +1063,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
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}
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DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
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DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
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// Find a register to spill.
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float minWeight = HUGE_VALF;
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@ -1121,16 +1130,19 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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--LastCandidate;
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}
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DOUT << "\t\tregister(s) with min weight(s): ";
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DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
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DOUT << tri_->getName(RegsWeights[i].first)
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<< " (" << RegsWeights[i].second << ")\n");
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DEBUG({
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errs() << "\t\tregister(s) with min weight(s): ";
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for (unsigned i = 0; i != LastCandidate; ++i)
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errs() << tri_->getName(RegsWeights[i].first)
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<< " (" << RegsWeights[i].second << ")\n";
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});
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// If the current has the minimum weight, we need to spill it and
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// add any added intervals back to unhandled, and restart
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// linearscan.
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if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
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DOUT << "\t\t\tspilling(c): " << *cur << '\n';
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DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
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SmallVector<LiveInterval*, 8> spillIs;
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std::vector<LiveInterval*> added;
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@ -1212,7 +1224,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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while (!spillIs.empty()) {
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LiveInterval *sli = spillIs.back();
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spillIs.pop_back();
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DOUT << "\t\t\tspilling(a): " << *sli << '\n';
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DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
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earliestStartInterval =
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(earliestStartInterval->beginNumber() < sli->beginNumber()) ?
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earliestStartInterval : sli;
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@ -1230,7 +1242,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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unsigned earliestStart = earliestStartInterval->beginNumber();
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DOUT << "\t\trolling back to: " << earliestStart << '\n';
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DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
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// Scan handled in reverse order up to the earliest start of a
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// spilled live interval and undo each one, restoring the state of
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@ -1240,7 +1252,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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// If this interval starts before t we are done.
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if (i->beginNumber() < earliestStart)
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break;
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DOUT << "\t\t\tundo changes for: " << *i << '\n';
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DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
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handled_.pop_back();
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// When undoing a live interval allocation we must know if it is active or
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@ -1290,7 +1302,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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LiveInterval *HI = handled_[i];
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if (!HI->expiredAt(earliestStart) &&
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HI->expiredAt(cur->beginNumber())) {
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DOUT << "\t\t\tundo changes for: " << *HI << '\n';
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DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
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active_.push_back(std::make_pair(HI, HI->begin()));
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assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
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addRegUse(vrm_->getPhys(HI->reg));
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@ -1419,7 +1431,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
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// available first.
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unsigned Preference = vrm_->getRegAllocPref(cur->reg);
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if (Preference) {
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DOUT << "(preferred: " << tri_->getName(Preference) << ") ";
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DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
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if (isRegAvail(Preference) &&
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RC->contains(Preference))
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return Preference;
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