mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ARM64: override all the things.
Actually, mostly only those in the top-level directory that already had a "virtual" attached. But it's the thought that counts and it's been a long day. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205131 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
b52cb5e0db
commit
c31891e350
@ -181,12 +181,12 @@ public:
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APInt &KnownOne, const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
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MVT getScalarShiftAmountTy(EVT LHSTy) const override;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
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bool *Fast = 0) const {
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bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
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bool *Fast = 0) const override {
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if (RequireStrictAlign)
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return false;
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// FIXME: True for Cyclone, but not necessary others.
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@ -196,40 +196,40 @@ public:
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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const char *getTargetNodeName(unsigned Opcode) const override;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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unsigned getFunctionAlignment(const Function *F) const;
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/// getMaximalGlobalOffset - Returns the maximal possible offset which can
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/// be used for loads / stores from the global.
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virtual unsigned getMaximalGlobalOffset() const;
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unsigned getMaximalGlobalOffset() const override;
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Addrspacecasts are always noops.
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return true;
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}
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) const;
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) const override;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/// isShuffleMaskLegal - Return true if the given shuffle mask can be
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/// codegen'd directly, or if it should be stack expanded.
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virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
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EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
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@ -249,52 +249,52 @@ public:
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MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const override;
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virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const override;
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virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
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virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
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virtual bool isZExtFree(EVT VT1, EVT VT2) const;
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virtual bool isZExtFree(SDValue Val, EVT VT2) const;
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bool isZExtFree(Type *Ty1, Type *Ty2) const override;
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bool isZExtFree(EVT VT1, EVT VT2) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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virtual bool hasPairedLoad(Type *LoadedType,
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unsigned &RequiredAligment) const;
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virtual bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const;
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bool hasPairedLoad(Type *LoadedType,
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unsigned &RequiredAligment) const override;
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bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
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virtual bool isLegalAddImmediate(int64_t) const;
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virtual bool isLegalICmpImmediate(int64_t) const;
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bool isLegalAddImmediate(int64_t) const override;
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bool isLegalICmpImmediate(int64_t) const override;
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset,
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bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
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/// \brief Return the cost of the scaling factor used in the addressing
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/// mode represented by AM for this target, for a load/store
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/// of the specified type.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, it returns a negative value.
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virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const;
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int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
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/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
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/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
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/// expanded to FMAs when this method returns true, otherwise fmuladd is
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/// expanded to fmul + fadd.
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virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const;
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const uint16_t *getScratchRegisters(CallingConv::ID CC) const override;
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virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const;
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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private:
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/// Subtarget - Keep a pointer to the ARM64Subtarget around so that we can
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@ -305,14 +305,14 @@ private:
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void addDRTypeForNEON(MVT VT);
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void addQRTypeForNEON(MVT VT);
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virtual SDValue
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SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SmallVectorImpl<SDValue> &InVals) const override;
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virtual SDValue LowerCall(CallLoweringInfo & /*CLI*/,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCall(CallLoweringInfo & /*CLI*/,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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@ -330,16 +330,15 @@ private:
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void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
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SDValue &Chain) const;
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virtual bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
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SelectionDAG &DAG) const;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
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SelectionDAG &DAG) const override;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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@ -42,17 +42,17 @@ public:
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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virtual const ARM64RegisterInfo &getRegisterInfo() const { return RI; }
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const ARM64RegisterInfo &getRegisterInfo() const { return RI; }
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DstReg, unsigned &SubIdx) const;
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bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DstReg, unsigned &SubIdx) const override;
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// \brief Does this instruction set its full destination register to zero?
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bool isGPRZero(const MachineInstr *MI) const;
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@ -75,18 +75,17 @@ public:
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/// Hint that pairing the given load or store is unprofitable.
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void suppressLdStPair(MachineInstr *MI) const;
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virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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unsigned &Offset,
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const TargetRegisterInfo *TRI) const;
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bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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unsigned &Offset,
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const TargetRegisterInfo *TRI) const override;
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virtual bool enableClusterLoads() const { return true; }
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bool enableClusterLoads() const override { return true; }
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virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
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MachineInstr *SecondLdSt,
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unsigned NumLoads) const;
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bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
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unsigned NumLoads) const override;
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virtual bool shouldScheduleAdjacent(MachineInstr *First,
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MachineInstr *Second) const;
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bool shouldScheduleAdjacent(MachineInstr *First,
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MachineInstr *Second) const override;
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MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
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uint64_t Offset, const MDNode *MDPtr,
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@ -95,60 +94,57 @@ public:
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc, unsigned Opcode,
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llvm::ArrayRef<unsigned> Indices) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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virtual MachineInstr *
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MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const override;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool canInsertSelect(const MachineBasicBlock &,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned, unsigned, int &, int &, int &) const;
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virtual void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned TrueReg, unsigned FalseReg) const;
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virtual void getNoopForMachoTarget(MCInst &NopInst) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool canInsertSelect(const MachineBasicBlock &,
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const SmallVectorImpl<MachineOperand> &Cond, unsigned,
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unsigned, int &, int &, int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc DL, unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned TrueReg, unsigned FalseReg) const override;
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void getNoopForMachoTarget(MCInst &NopInst) const override;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
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/// Return true if the comparison instruction can be analyzed.
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virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const;
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bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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/// optimizeCompareInstr - Convert the instruction supplying the argument to
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/// the comparison into one that sets the zero bit in the flags register.
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virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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private:
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void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
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@ -33,10 +33,12 @@ private:
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public:
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ARM64RegisterInfo(const ARM64InstrInfo *tii, const ARM64Subtarget *sti);
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/// Code Generation virtual methods...
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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/// Code Generation virtual methods...
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const uint16_t *
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getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
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// Calls involved in thread-local variable lookup save more registers than
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// normal calls, so they need a different mask to represent this.
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@ -52,36 +54,39 @@ public:
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/// this property
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const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool useFPForScavengingIndex(const MachineFunction &MF) const;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
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bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI,
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int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
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int FrameIdx, int64_t Offset) const;
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int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineBasicBlock::iterator I, unsigned BaseReg,
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int64_t Offset) const;
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int64_t Offset) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = NULL) const;
|
||||
|
||||
RegScavenger *RS = NULL) const override;
|
||||
bool cannotEliminateFrame(const MachineFunction &MF) const;
|
||||
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
|
||||
|
||||
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
|
||||
bool hasBasePointer(const MachineFunction &MF) const;
|
||||
unsigned getBaseRegister() const;
|
||||
|
||||
// Debug information queries.
|
||||
unsigned getFrameRegister(const MachineFunction &MF) const;
|
||||
unsigned getFrameRegister(const MachineFunction &MF) const override;
|
||||
|
||||
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
||||
MachineFunction &MF) const;
|
||||
MachineFunction &MF) const override;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
@ -27,11 +27,10 @@ public:
|
||||
explicit ARM64SelectionDAGInfo(const TargetMachine &TM);
|
||||
~ARM64SelectionDAGInfo();
|
||||
|
||||
virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
|
||||
SDValue Chain, SDValue Dst,
|
||||
SDValue Src, SDValue Size,
|
||||
unsigned Align, bool isVolatile,
|
||||
MachinePointerInfo DstPtrInfo) const;
|
||||
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
|
||||
SDValue Dst, SDValue Src, SDValue Size,
|
||||
unsigned Align, bool isVolatile,
|
||||
MachinePointerInfo DstPtrInfo) const override;
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
@ -45,7 +45,7 @@ public:
|
||||
ARM64Subtarget(const std::string &TT, const std::string &CPU,
|
||||
const std::string &FS);
|
||||
|
||||
virtual bool enableMachineScheduler() const { return true; }
|
||||
bool enableMachineScheduler() const override { return true; }
|
||||
|
||||
bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
|
||||
|
||||
|
||||
@ -41,27 +41,27 @@ public:
|
||||
const TargetOptions &Options, Reloc::Model RM,
|
||||
CodeModel::Model CM, CodeGenOpt::Level OL);
|
||||
|
||||
virtual const ARM64Subtarget *getSubtargetImpl() const { return &Subtarget; }
|
||||
virtual const ARM64TargetLowering *getTargetLowering() const {
|
||||
const ARM64Subtarget *getSubtargetImpl() const override { return &Subtarget; }
|
||||
const ARM64TargetLowering *getTargetLowering() const override {
|
||||
return &TLInfo;
|
||||
}
|
||||
virtual const DataLayout *getDataLayout() const { return &DL; }
|
||||
virtual const ARM64FrameLowering *getFrameLowering() const {
|
||||
const DataLayout *getDataLayout() const override { return &DL; }
|
||||
const ARM64FrameLowering *getFrameLowering() const override {
|
||||
return &FrameLowering;
|
||||
}
|
||||
virtual const ARM64InstrInfo *getInstrInfo() const { return &InstrInfo; }
|
||||
virtual const ARM64RegisterInfo *getRegisterInfo() const {
|
||||
const ARM64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
|
||||
const ARM64RegisterInfo *getRegisterInfo() const override {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
virtual const ARM64SelectionDAGInfo *getSelectionDAGInfo() const {
|
||||
const ARM64SelectionDAGInfo *getSelectionDAGInfo() const override {
|
||||
return &TSInfo;
|
||||
}
|
||||
|
||||
// Pass Pipeline Configuration
|
||||
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
|
||||
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
||||
|
||||
/// \brief Register ARM64 analysis passes with a pass manager.
|
||||
virtual void addAnalysisPasses(PassManagerBase &PM);
|
||||
void addAnalysisPasses(PassManagerBase &PM) override;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
@ -18,7 +18,7 @@ class ARM64TargetMachine;
|
||||
|
||||
/// This implementation is used for AArch64 ELF targets (Linux in particular).
|
||||
class ARM64_ELFTargetObjectFile : public TargetLoweringObjectFileELF {
|
||||
virtual void Initialize(MCContext &Ctx, const TargetMachine &TM);
|
||||
void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
|
||||
};
|
||||
|
||||
/// ARM64_MachoTargetObjectFile - This TLOF implementation is used for Darwin.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user