6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-26 23:24:34 +00:00
Code Issues Projects Releases Wiki Activity

A7.3 register encoding

Browse Source 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-05 22:57:07 +00:00
parent da19475328
commit c3281c10c9
3 changed files with 21 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -94,6 +94,16 @@ getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
}
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
// A7.3 register encoding
// Qd -> bit[12] == 0
// Qn -> bit[16] == 0
// Qm -> bit[0] == 0
//
// If one of these bits is 1, the instruction is UNDEFINED.
if (RegClassID == ARM::QPRRegClassID && slice(RawRegister, 0, 0) == 1) {
B->SetErr(-1);
return 0;
}
unsigned RegNum =
RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;