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Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was

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no pattern.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-10-16 10:02:06 +00:00
parent 9cabfa6842
commit c32a8c9073
2 changed files with 9 additions and 3 deletions
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8
lib/Target/CellSPU/SPUISelLowering.cpp
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@ -1752,9 +1752,11 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
// Both upper and lower are special, lower to a constant pool load:
if (lower_special && upper_special) {
SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
SplatValCN, SplatValCN);
SDValue UpperVal = DAG.getConstant(upper, MVT::i32);
SDValue LowerVal = DAG.getConstant(lower, MVT::i32);
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
UpperVal, LowerVal, UpperVal, LowerVal);
return DAG.getNode(ISD::BITCAST, dl, OpVT, BV);
}
SDValue LO32;

4
test/CodeGen/CellSPU/shift_ops.ll
View File

@ -342,3 +342,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
%rv = ashr <8 x i16> %val, %sh
ret <8 x i16> %rv
}
define <2 x i64> @special_const() {
ret <2 x i64> <i64 4294967295, i64 4294967295>
}