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[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1183,6 +1183,35 @@ public:
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return false;
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}
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/// Return true if the target supplies and combines to a paired load
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/// two loaded values of type LoadedType next to each other in memory.
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/// RequiredAlignment gives the minimal alignment constraints that must be met to
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/// be able to select this paired load.
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///
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/// This information is *not* used to generate actual paired loads, but it is used
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/// to generate a sequence of loads that is easier to combine into a paired load.
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/// For instance, something like this:
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/// a = load i64* addr
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/// b = trunc i64 a to i32
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/// c = lshr i64 a, 32
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/// d = trunc i64 c to i32
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/// will be optimized into:
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/// b = load i32* addr1
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/// d = load i32* addr2
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/// Where addr1 = addr2 +/- sizeof(i32).
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///
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/// In other words, unless the target performs a post-isel load combining, this
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/// information should not be provided because it will generate more loads.
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virtual bool hasPairedLoad(Type * /*LoadedType*/,
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unsigned & /*RequiredAligment*/) const {
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return false;
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}
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virtual bool hasPairedLoad(EVT /*LoadedType*/,
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unsigned & /*RequiredAligment*/) const {
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return false;
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}
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/// Return true if zero-extending the specific node Val to type VT2 is free
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/// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
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/// because it's folded such as X86 zero-extending loads).
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