mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Modified graph construction to use one pass to find all defs.
Avoids having to handle some special cases that cause complex interactions with instr. selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1138 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
df1c3b8398
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c352d2c530
@ -24,19 +24,30 @@
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#include "llvm/Support/StringExtras.h"
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#include "llvm/iOther.h"
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#include <algorithm>
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#include <hash_map>
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#include <vector>
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//*********************** Internal Data Structures *************************/
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typedef vector< pair<SchedGraphNode*, unsigned int> > RefVec;
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// The following two types need to be classes, not typedefs, so we can use
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// opaque declarations in SchedGraph.h
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//
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struct RefVec: public vector< pair<SchedGraphNode*, int> > {
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typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
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typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
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};
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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struct RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
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typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
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typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphEdge
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//
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@ -599,7 +610,11 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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}
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}
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#undef OLD_SSA_EDGE_CONSTRUCTION
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#ifdef OLD_SSA_EDGE_CONSTRUCTION
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//
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// Delete this code once a few more tests pass.
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//
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inline void
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CreateSSAEdge(SchedGraph* graph,
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MachineInstr* defInstr,
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@ -668,10 +683,23 @@ SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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}
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}
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#endif OLD_SSA_EDGE_CONSTRUCTION
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void
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SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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const RefVec& defVec,
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const Value* defValue,
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const TargetMachine& target)
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{
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for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
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(void) new SchedGraphEdge((*I).first, destNode, defValue);
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}
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void
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SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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RegToRefVecMap& regToRefVecMap,
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const ValueToDefVecMap& valueToDefVecMap,
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const TargetMachine& target)
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{
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SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
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@ -682,25 +710,15 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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const Instruction* instr = node->getInstr();
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// Add edges for all operands of the machine instruction.
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// Also, record all machine register references to add reg. deps. later.
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//
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for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
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{
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const MachineOperand& mop = minstr.getOperand(i);
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// if this writes to a machine register other than the hardwired
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// "zero" register, record the reference.
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if (mop.getOperandType() == MachineOperand::MO_MachineRegister
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&& (mop.getMachineRegNum()
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!= (unsigned) target.getRegInfo().getZeroRegNum()))
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{
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regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
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}
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// ignore all other def operands
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// ignore def operands here
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if (minstr.operandIsDefined(i))
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continue;
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const MachineOperand& mop = minstr.getOperand(i);
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switch(mop.getOperandType())
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{
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case MachineOperand::MO_VirtualRegister:
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@ -708,9 +726,9 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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if (const Instruction* srcI =
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dyn_cast_or_null<Instruction>(mop.getVRegValue()))
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{
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if (srcI->getOpcode() == TMP_INSTRUCTION_OPCODE)
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srcI = instr;
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addSSAEdge(node, srcI, mop.getVRegValue(), target);
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ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
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if (I != valueToDefVecMap.end())
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addSSAEdge(node, (*I).second, mop.getVRegValue(), target);
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}
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break;
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@ -737,9 +755,9 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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if (const Instruction* srcI =
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dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
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{
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if (srcI->getOpcode() == TMP_INSTRUCTION_OPCODE)
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srcI = instr;
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addSSAEdge(node, srcI, minstr.getImplicitRef(i), target);
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ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
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if (I != valueToDefVecMap.end())
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addSSAEdge(node, (*I).second, minstr.getImplicitRef(i), target);
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}
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}
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@ -758,11 +776,11 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
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{
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const MachineOperand& op = mvec[i]->getOperand(o);
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const MachineOperand& mop = mvec[i]->getOperand(o);
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if ((op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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op.getOperandType() == MachineOperand::MO_CCRegister)
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&& op.getVRegValue() == (Value*) instr)
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if ((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
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mop.getOperandType() == MachineOperand::MO_CCRegister)
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&& mop.getVRegValue() == (Value*) instr)
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{
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// this operand is a definition or use of value `instr'
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SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
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@ -796,9 +814,64 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
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}
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void
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SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
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SchedGraphNode* node,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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// Collect the register references and value defs. for explicit operands
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//
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const MachineInstr& minstr = * node->getMachineInstr();
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for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
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{
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const MachineOperand& mop = minstr.getOperand(i);
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// if this references a register other than the hardwired
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// "zero" register, record the reference.
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if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
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{
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int regNum = mop.getMachineRegNum();
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if (regNum != target.getRegInfo().getZeroRegNum())
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regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
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continue; // nothing more to do
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}
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// ignore all other non-def operands
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if (! minstr.operandIsDefined(i))
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continue;
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// We must be defining a value.
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assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
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mop.getOperandType() == MachineOperand::MO_CCRegister)
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&& "Do not expect any other kind of operand to be defined!");
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const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
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valueToDefVecMap[defInstr].push_back(make_pair(node, i));
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}
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//
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// Collect value defs. for implicit operands. The interface to extract
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// them assumes they must be virtual registers!
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//
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for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
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if (minstr.implicitRefIsDefined(i))
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if (const Instruction* defInstr =
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dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
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{
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valueToDefVecMap[defInstr].push_back(make_pair(node, -i));
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}
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}
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void
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SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
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const Instruction* instr)
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const Instruction* instr,
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vector<const Instruction*>& memVec,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
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@ -808,7 +881,16 @@ SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
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SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
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instr, mvec[i], target);
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this->noteGraphNodeForInstr(mvec[i], node);
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// Remember all register references and value defs
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findDefUseInfoAtInstr(target, node, regToRefVecMap, valueToDefVecMap);
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}
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// Remember load/store/call instructions to add memory deps later.
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if (instr->getOpcode() == Instruction::Load ||
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instr->getOpcode() == Instruction::Store ||
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instr->getOpcode() == Instruction::Call)
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memVec.push_back(instr);
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}
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@ -820,12 +902,18 @@ SchedGraph::buildGraph(const TargetMachine& target)
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assert(bbVec.size() == 1 && "Only handling a single basic block here");
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// Use these data structures to note all LLVM memory instructions.
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// Use this data structure to note all machine operands that compute
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// ordinary LLVM values. These must be computed defs (i.e., instructions).
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// Note that there may be multiple machine instructions that define
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// each Value.
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ValueToDefVecMap valueToDefVecMap;
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// Use this data structure to note all LLVM memory instructions.
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// We use this to add memory dependence edges without a second full walk.
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//
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vector<const Instruction*> memVec;
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// Use this data structures to note any uses or definitions of
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// Use this data structure to note any uses or definitions of
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// machine registers so we can add edges for those later without
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// extra passes over the nodes.
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// The vector holds an ordered list of references to the machine reg,
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@ -850,14 +938,10 @@ SchedGraph::buildGraph(const TargetMachine& target)
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{
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const Instruction *instr = *II;
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// Build graph nodes for this VM instruction
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buildNodesforVMInstr(target, instr);
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// Remember the load/store/call instructions to add memory deps later.
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if (instr->getOpcode() == Instruction::Load ||
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instr->getOpcode() == Instruction::Store ||
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instr->getOpcode() == Instruction::Call)
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memVec.push_back(instr);
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// Build graph nodes for this VM instruction and gather def/use info.
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// Do these together in a single pass over all machine instructions.
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buildNodesforVMInstr(target, instr,
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memVec, regToRefVecMap, valueToDefVecMap);
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}
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//----------------------------------------------------------------
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@ -888,22 +972,16 @@ SchedGraph::buildGraph(const TargetMachine& target)
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// Then add edges between call instructions and CC set/use instructions
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this->addCallCCEdges(memVec, bbMvec, target);
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// Then add other edges for all instructions in the block.
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// Do this in machine code order and find all references to machine regs.
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// Then add incoming def-use (SSA) edges for each machine instruction.
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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addEdgesForInstruction(*bbMvec[i], regToRefVecMap, target);
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addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
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// Since the code is no longer in SSA form, add output dep. edges
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// between machine instructions that define the same Value, and anti-dep.
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// edges from those to other machine instructions for the same VM instr.
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// Then add non-SSA edges for all VM instructions in the block.
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// We assume that all machine instructions that define a value are
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// generated from the VM instruction corresponding to that value.
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//
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// TODO: This could probably be done much more efficiently.
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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{
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const Instruction *instr = *II;
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this->addNonSSAEdgesForValue(instr, target);
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}
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this->addNonSSAEdgesForValue(*II, target);
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// Then add edges for dependences on machine registers
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this->addMachineRegEdges(regToRefVecMap, target);
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@ -34,6 +34,8 @@ class SchedGraphEdge;
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class SchedGraphNode;
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class SchedGraph;
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class RegToRefVecMap;
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class ValueToDefVecMap;
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class RefVec;
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class MachineInstr;
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class MachineCodeForBasicBlock;
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@ -299,11 +301,19 @@ private:
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void buildGraph (const TargetMachine& target);
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void buildNodesforVMInstr (const TargetMachine& target,
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const Instruction* instr);
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const Instruction* instr,
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vector<const Instruction*>& memVec,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap);
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void findDefUseInfoAtInstr (const TargetMachine& target,
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SchedGraphNode* node,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap);
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void addEdgesForInstruction (const MachineInstr& minstr,
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RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target);
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const ValueToDefVecMap& valueToDefVecMap,
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const TargetMachine& target);
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void addCDEdges (const TerminatorInst* term,
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const TargetMachine& target);
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@ -319,7 +329,7 @@ private:
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const TargetMachine& target);
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void addSSAEdge (SchedGraphNode* node,
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const Instruction* defVMInstr,
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const RefVec& defVec,
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const Value* defValue,
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const TargetMachine& target);
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@ -24,19 +24,30 @@
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#include "llvm/Support/StringExtras.h"
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#include "llvm/iOther.h"
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#include <algorithm>
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#include <hash_map>
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#include <vector>
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//*********************** Internal Data Structures *************************/
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typedef vector< pair<SchedGraphNode*, unsigned int> > RefVec;
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// The following two types need to be classes, not typedefs, so we can use
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// opaque declarations in SchedGraph.h
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//
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struct RefVec: public vector< pair<SchedGraphNode*, int> > {
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typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
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typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
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};
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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struct RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
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typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
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typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphEdge
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//
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@ -599,7 +610,11 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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}
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}
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#undef OLD_SSA_EDGE_CONSTRUCTION
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#ifdef OLD_SSA_EDGE_CONSTRUCTION
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//
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// Delete this code once a few more tests pass.
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//
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inline void
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CreateSSAEdge(SchedGraph* graph,
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MachineInstr* defInstr,
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@ -668,10 +683,23 @@ SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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}
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}
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#endif OLD_SSA_EDGE_CONSTRUCTION
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void
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SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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const RefVec& defVec,
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const Value* defValue,
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const TargetMachine& target)
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{
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for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
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(void) new SchedGraphEdge((*I).first, destNode, defValue);
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}
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void
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SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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RegToRefVecMap& regToRefVecMap,
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const ValueToDefVecMap& valueToDefVecMap,
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const TargetMachine& target)
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{
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SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
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@ -682,25 +710,15 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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const Instruction* instr = node->getInstr();
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// Add edges for all operands of the machine instruction.
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// Also, record all machine register references to add reg. deps. later.
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//
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for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
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{
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const MachineOperand& mop = minstr.getOperand(i);
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// if this writes to a machine register other than the hardwired
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// "zero" register, record the reference.
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if (mop.getOperandType() == MachineOperand::MO_MachineRegister
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&& (mop.getMachineRegNum()
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!= (unsigned) target.getRegInfo().getZeroRegNum()))
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{
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regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
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}
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// ignore all other def operands
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// ignore def operands here
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if (minstr.operandIsDefined(i))
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continue;
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const MachineOperand& mop = minstr.getOperand(i);
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switch(mop.getOperandType())
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{
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case MachineOperand::MO_VirtualRegister:
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@ -708,9 +726,9 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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if (const Instruction* srcI =
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dyn_cast_or_null<Instruction>(mop.getVRegValue()))
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{
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if (srcI->getOpcode() == TMP_INSTRUCTION_OPCODE)
|
||||
srcI = instr;
|
||||
addSSAEdge(node, srcI, mop.getVRegValue(), target);
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addSSAEdge(node, (*I).second, mop.getVRegValue(), target);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -737,9 +755,9 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
||||
if (const Instruction* srcI =
|
||||
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
|
||||
{
|
||||
if (srcI->getOpcode() == TMP_INSTRUCTION_OPCODE)
|
||||
srcI = instr;
|
||||
addSSAEdge(node, srcI, minstr.getImplicitRef(i), target);
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addSSAEdge(node, (*I).second, minstr.getImplicitRef(i), target);
|
||||
}
|
||||
}
|
||||
|
||||
@ -758,11 +776,11 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
||||
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
||||
for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
|
||||
{
|
||||
const MachineOperand& op = mvec[i]->getOperand(o);
|
||||
const MachineOperand& mop = mvec[i]->getOperand(o);
|
||||
|
||||
if ((op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
op.getOperandType() == MachineOperand::MO_CCRegister)
|
||||
&& op.getVRegValue() == (Value*) instr)
|
||||
if ((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
mop.getOperandType() == MachineOperand::MO_CCRegister)
|
||||
&& mop.getVRegValue() == (Value*) instr)
|
||||
{
|
||||
// this operand is a definition or use of value `instr'
|
||||
SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
|
||||
@ -796,9 +814,64 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
|
||||
SchedGraphNode* node,
|
||||
RegToRefVecMap& regToRefVecMap,
|
||||
ValueToDefVecMap& valueToDefVecMap)
|
||||
{
|
||||
const MachineInstrInfo& mii = target.getInstrInfo();
|
||||
|
||||
// Collect the register references and value defs. for explicit operands
|
||||
//
|
||||
const MachineInstr& minstr = * node->getMachineInstr();
|
||||
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
|
||||
{
|
||||
const MachineOperand& mop = minstr.getOperand(i);
|
||||
|
||||
// if this references a register other than the hardwired
|
||||
// "zero" register, record the reference.
|
||||
if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
|
||||
{
|
||||
int regNum = mop.getMachineRegNum();
|
||||
if (regNum != target.getRegInfo().getZeroRegNum())
|
||||
regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
|
||||
continue; // nothing more to do
|
||||
}
|
||||
|
||||
// ignore all other non-def operands
|
||||
if (! minstr.operandIsDefined(i))
|
||||
continue;
|
||||
|
||||
// We must be defining a value.
|
||||
assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
mop.getOperandType() == MachineOperand::MO_CCRegister)
|
||||
&& "Do not expect any other kind of operand to be defined!");
|
||||
|
||||
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
|
||||
valueToDefVecMap[defInstr].push_back(make_pair(node, i));
|
||||
}
|
||||
|
||||
//
|
||||
// Collect value defs. for implicit operands. The interface to extract
|
||||
// them assumes they must be virtual registers!
|
||||
//
|
||||
for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
|
||||
if (minstr.implicitRefIsDefined(i))
|
||||
if (const Instruction* defInstr =
|
||||
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
|
||||
{
|
||||
valueToDefVecMap[defInstr].push_back(make_pair(node, -i));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
|
||||
const Instruction* instr)
|
||||
const Instruction* instr,
|
||||
vector<const Instruction*>& memVec,
|
||||
RegToRefVecMap& regToRefVecMap,
|
||||
ValueToDefVecMap& valueToDefVecMap)
|
||||
{
|
||||
const MachineInstrInfo& mii = target.getInstrInfo();
|
||||
const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
||||
@ -808,7 +881,16 @@ SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
|
||||
SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
|
||||
instr, mvec[i], target);
|
||||
this->noteGraphNodeForInstr(mvec[i], node);
|
||||
|
||||
// Remember all register references and value defs
|
||||
findDefUseInfoAtInstr(target, node, regToRefVecMap, valueToDefVecMap);
|
||||
}
|
||||
|
||||
// Remember load/store/call instructions to add memory deps later.
|
||||
if (instr->getOpcode() == Instruction::Load ||
|
||||
instr->getOpcode() == Instruction::Store ||
|
||||
instr->getOpcode() == Instruction::Call)
|
||||
memVec.push_back(instr);
|
||||
}
|
||||
|
||||
|
||||
@ -820,12 +902,18 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
|
||||
assert(bbVec.size() == 1 && "Only handling a single basic block here");
|
||||
|
||||
// Use these data structures to note all LLVM memory instructions.
|
||||
// Use this data structure to note all machine operands that compute
|
||||
// ordinary LLVM values. These must be computed defs (i.e., instructions).
|
||||
// Note that there may be multiple machine instructions that define
|
||||
// each Value.
|
||||
ValueToDefVecMap valueToDefVecMap;
|
||||
|
||||
// Use this data structure to note all LLVM memory instructions.
|
||||
// We use this to add memory dependence edges without a second full walk.
|
||||
//
|
||||
vector<const Instruction*> memVec;
|
||||
|
||||
// Use this data structures to note any uses or definitions of
|
||||
// Use this data structure to note any uses or definitions of
|
||||
// machine registers so we can add edges for those later without
|
||||
// extra passes over the nodes.
|
||||
// The vector holds an ordered list of references to the machine reg,
|
||||
@ -850,14 +938,10 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
{
|
||||
const Instruction *instr = *II;
|
||||
|
||||
// Build graph nodes for this VM instruction
|
||||
buildNodesforVMInstr(target, instr);
|
||||
|
||||
// Remember the load/store/call instructions to add memory deps later.
|
||||
if (instr->getOpcode() == Instruction::Load ||
|
||||
instr->getOpcode() == Instruction::Store ||
|
||||
instr->getOpcode() == Instruction::Call)
|
||||
memVec.push_back(instr);
|
||||
// Build graph nodes for this VM instruction and gather def/use info.
|
||||
// Do these together in a single pass over all machine instructions.
|
||||
buildNodesforVMInstr(target, instr,
|
||||
memVec, regToRefVecMap, valueToDefVecMap);
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------
|
||||
@ -888,22 +972,16 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
// Then add edges between call instructions and CC set/use instructions
|
||||
this->addCallCCEdges(memVec, bbMvec, target);
|
||||
|
||||
// Then add other edges for all instructions in the block.
|
||||
// Do this in machine code order and find all references to machine regs.
|
||||
// Then add incoming def-use (SSA) edges for each machine instruction.
|
||||
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
|
||||
addEdgesForInstruction(*bbMvec[i], regToRefVecMap, target);
|
||||
addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
|
||||
|
||||
// Since the code is no longer in SSA form, add output dep. edges
|
||||
// between machine instructions that define the same Value, and anti-dep.
|
||||
// edges from those to other machine instructions for the same VM instr.
|
||||
// Then add non-SSA edges for all VM instructions in the block.
|
||||
// We assume that all machine instructions that define a value are
|
||||
// generated from the VM instruction corresponding to that value.
|
||||
//
|
||||
// TODO: This could probably be done much more efficiently.
|
||||
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
||||
{
|
||||
const Instruction *instr = *II;
|
||||
this->addNonSSAEdgesForValue(instr, target);
|
||||
}
|
||||
this->addNonSSAEdgesForValue(*II, target);
|
||||
|
||||
// Then add edges for dependences on machine registers
|
||||
this->addMachineRegEdges(regToRefVecMap, target);
|
||||
|
@ -34,6 +34,8 @@ class SchedGraphEdge;
|
||||
class SchedGraphNode;
|
||||
class SchedGraph;
|
||||
class RegToRefVecMap;
|
||||
class ValueToDefVecMap;
|
||||
class RefVec;
|
||||
class MachineInstr;
|
||||
class MachineCodeForBasicBlock;
|
||||
|
||||
@ -299,11 +301,19 @@ private:
|
||||
void buildGraph (const TargetMachine& target);
|
||||
|
||||
void buildNodesforVMInstr (const TargetMachine& target,
|
||||
const Instruction* instr);
|
||||
const Instruction* instr,
|
||||
vector<const Instruction*>& memVec,
|
||||
RegToRefVecMap& regToRefVecMap,
|
||||
ValueToDefVecMap& valueToDefVecMap);
|
||||
|
||||
void findDefUseInfoAtInstr (const TargetMachine& target,
|
||||
SchedGraphNode* node,
|
||||
RegToRefVecMap& regToRefVecMap,
|
||||
ValueToDefVecMap& valueToDefVecMap);
|
||||
|
||||
void addEdgesForInstruction (const MachineInstr& minstr,
|
||||
RegToRefVecMap& regToRefVecMap,
|
||||
const TargetMachine& target);
|
||||
const ValueToDefVecMap& valueToDefVecMap,
|
||||
const TargetMachine& target);
|
||||
|
||||
void addCDEdges (const TerminatorInst* term,
|
||||
const TargetMachine& target);
|
||||
@ -319,7 +329,7 @@ private:
|
||||
const TargetMachine& target);
|
||||
|
||||
void addSSAEdge (SchedGraphNode* node,
|
||||
const Instruction* defVMInstr,
|
||||
const RefVec& defVec,
|
||||
const Value* defValue,
|
||||
const TargetMachine& target);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user