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Add missing patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51435 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2351,6 +2351,12 @@ def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(v4i32 (X86vzmovl (v4i32 (scalar_to_vector
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(v4i32 (X86vzmovl (v4i32 (scalar_to_vector
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(loadi32 addr:$src))))))]>;
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(loadi32 addr:$src))))))]>;
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def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
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(MOVZDI2PDIrm addr:$src)>;
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def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
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(MOVZDI2PDIrm addr:$src)>;
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def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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@ -2358,6 +2364,10 @@ def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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(loadi64 addr:$src))))))]>, XS,
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(loadi64 addr:$src))))))]>, XS,
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Requires<[HasSSE2]>;
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Requires<[HasSSE2]>;
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def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
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(MOVZQI2PQIrm addr:$src)>;
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def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
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(MOVZQI2PQIrm addr:$src)>;
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def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
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def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
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}
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}
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10
test/CodeGen/X86/vec_set-I.ll
Normal file
10
test/CodeGen/X86/vec_set-I.ll
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@ -0,0 +1,10 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep xorp
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define void @t1() nounwind {
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%tmp298.i.i = load <4 x float>* null, align 16
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%tmp304.i.i = bitcast <4 x float> %tmp298.i.i to <4 x i32>
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%tmp305.i.i = and <4 x i32> %tmp304.i.i, < i32 -1, i32 0, i32 0, i32 0 >
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store <4 x i32> %tmp305.i.i, <4 x i32>* null, align 16
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unreachable
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}
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