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Feedback from Nate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23767 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -205,7 +205,10 @@ instructions.</li>
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<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
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phase takes the DAG of target instructions produced by the instruction selection
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phase, determines an ordering of the instructions, then emits the instructions
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as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
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as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
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that we describe this in the <a href="#instselect">instruction selection
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section</a> because it operates on a <a
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href="#selectiondag_intro">SelectionDAG</a>.
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</li>
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<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
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@ -1110,6 +1113,10 @@ converted to a list of <a href="#machineinstr">MachineInstr</a>s and the
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Selection DAG is destroyed.
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</p>
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<p>Note that this phase is logically seperate from the instruction selection
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phase, but is tied to it closely in the code because it operates on
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SelectionDAGs.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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