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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23767 91177308-0d34-0410-b5e6-96231b3b80d8
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Chris Lattner 2005-10-17 03:09:31 +00:00
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@ -205,7 +205,10 @@ instructions.</li>
<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
phase takes the DAG of target instructions produced by the instruction selection
phase, determines an ordering of the instructions, then emits the instructions
as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
that we describe this in the <a href="#instselect">instruction selection
section</a> because it operates on a <a
href="#selectiondag_intro">SelectionDAG</a>.
</li>
<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
@ -1110,6 +1113,10 @@ converted to a list of <a href="#machineinstr">MachineInstr</a>s and the
Selection DAG is destroyed.
</p>
<p>Note that this phase is logically seperate from the instruction selection
phase, but is tied to it closely in the code because it operates on
SelectionDAGs.</p>
</div>
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