Update this significantly, mention subtarget and isel generation support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23760 91177308-0d34-0410-b5e6-96231b3b80d8

docs/WritingAnLLVMBackend.html

@@ -68,21 +68,21 @@ convert the LLVM representation to machine assembly code or other languages.</p>
 implement the following:</p>
 
 <ul>
-<li>Describe the register set
+<li>Describe the register set.
   <ul>
   <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
       the register set and register classes</li>
   <li>Implement a subclass of <tt><a
       href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li>
   </ul></li>
-<li>Describe the instruction set
+<li>Describe the instruction set.
   <ul>
   <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
       the instruction set</li>
   <li>Implement a subclass of <tt><a
       href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li>
   </ul></li>
-<li>Describe the target machine
+<li>Describe the target machine.
   <ul>
   <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
       the target that describes the pointer size and references the instruction
@@ -104,38 +104,37 @@ RegisterTarget&lt;<em>MyTargetMachine</em>&gt; M("short_name", "  Target name");
       is the description of your target to appear in <tt>-help</tt>
       listing.</li>
   </ul></li>
-<li>Implement the assembly printer for the architecture.  Usually, if you have
+<li>Implement the assembly printer for the architecture.
-described the instruction set with the assembly printer generator in mind, that
+  <ul>
-step can be almost automated.</li>
+  <li>Define all of the assembly strings for your target, adding them to the
-</ul>
+      instructions in your *InstrInfo.td file.</li>
-
+  <li>Implement the <tt>llvm::AsmPrinter</tt> interface.</li>
-<p>You also need to write an instruction selector for your platform.  The
+  </ul>
-recommended method is the <a
+</li>
-href="CodeGenerator.html#instselect">pattern-matching instruction selector</a>,
+<li>Implement an instruction selector for the architecture.
-examples of which you can see in other targets:
+  <ul>
-<tt>lib/Target/*/*ISelPattern.cpp</tt>.  The former method for writing
+  <li>The recommended method is the <a href="CodeGenerator.html#instselect">
-instruction selectors (<b>not</b> recommended for new targets) is evident in
+      pattern-matching DAG-to-DAG instruction selector</a> (for example, see
-<tt>lib/Target/*/*ISelSimple.cpp</tt>, which are <tt>InstVisitor</tt>-based
+      the PowerPC backend in PPCISelDAGtoDAG.cpp).  Parts of instruction
-translators, generating code for an LLVM instruction at a time.  Creating an
+      selector creation can be performed by adding patterns to the instructions
-instruction selector is perhaps the most time-consuming part of creating a
+      in your <tt>.td</tt> file.</li>
-back-end.</p>
+  </ul>
-
+</li>
-<p>To create a JIT for your platform:</p>
+<li>Optionally, add subtarget support.
-
 <ul>
-<li>Create a subclass of <tt><a
+  <li>If your target has multiple subtargets (e.g. variants with different
-    href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
+      capabilities), implement the <tt>llvm::TargetSubtarget</tt> interface
-<li>Create a machine code emitter that will be used to emit binary code
+      for your architecture.  This allows you to add <tt>-mcpu=</tt> and 
-    directly into memory, given <tt>MachineInstr</tt>s</li>
+      <tt>-mattr=</tt> options.</li>
+</ul>
+<li>Optionally, add JIT support.
+  <ul>
+  <li>Create a subclass of <tt><a
+      href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
+  <li>Create a machine code emitter that will be used to emit binary code
+      directly into memory, given <tt>MachineInstr</tt>s</li>
+  </ul>
 </ul>
-
-<p>Note that <tt>lib/target/Skeleton</tt> is a clean skeleton for a new target,
-so you might want to start with that and adapt it for your target, and if you
-are wondering how things are done, peek in the X86 or PowerPC target.</p>
-
-<p>The Skeleton target is non-functional but provides the basic building blocks
-you will need for your endeavor.</p>
-
 </div>
 
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