From c3c021bcadd580a0764e12527f58a94389ae81ce Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 19 Jan 2005 17:24:34 +0000 Subject: [PATCH] Fix a problem where were were literally selecting for INCREASED register pressure, not decreases register pressure. Fix problem where we accidentally swapped the operands of SHLD, which caused fourinarow to fail. This fixes fourinarow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19697 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelPattern.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index 574cbf7654c..901077b24ad 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -1185,11 +1185,11 @@ bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) { } else if (RegSize != 8) { unsigned AReg, BReg; if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) { - AReg = SelectExpr(ShrVal); BReg = SelectExpr(ShlVal); + AReg = SelectExpr(ShrVal); } else { - BReg = SelectExpr(ShlVal); AReg = SelectExpr(ShrVal); + BReg = SelectExpr(ShlVal); } unsigned ShAmt = SelectExpr(ShrAmt); BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt); @@ -1221,11 +1221,11 @@ bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) { } else if (RegSize != 8) { unsigned AReg, BReg; if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) { - AReg = SelectExpr(ShrVal); - BReg = SelectExpr(ShlVal); + AReg = SelectExpr(ShlVal); + BReg = SelectExpr(ShrVal); } else { - BReg = SelectExpr(ShlVal); - AReg = SelectExpr(ShrVal); + BReg = SelectExpr(ShrVal); + AReg = SelectExpr(ShlVal); } unsigned ShAmt = SelectExpr(ShlAmt); BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt); @@ -1250,11 +1250,11 @@ bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) { } else if (RegSize != 8) { unsigned AReg, BReg; if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) { - AReg = SelectExpr(ShrVal); BReg = SelectExpr(ShlVal); + AReg = SelectExpr(ShrVal); } else { - BReg = SelectExpr(ShlVal); AReg = SelectExpr(ShrVal); + BReg = SelectExpr(ShlVal); } unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8; BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)