From c3de802ad9f0dbbb5c6531b0d30fbe96fc3c36c4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 16 Jun 2008 22:52:53 +0000 Subject: [PATCH] Do not issue identity copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52373 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LowerSubregs.cpp | 35 ++++++++++++++--------- test/CodeGen/X86/2008-06-16-SubregsBug.ll | 14 +++++++++ 2 files changed, 36 insertions(+), 13 deletions(-) create mode 100644 test/CodeGen/X86/2008-06-16-SubregsBug.ll diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 0710a353006..296e6d45c34 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -108,15 +108,20 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { DOUT << "subreg: CONVERTING: " << *MI; - // Insert sub-register copy - const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg); - const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + if (DstSubReg == InsReg) { + // No need to insert an identify copy instruction. + DOUT << "subreg: eliminated!"; + } else { + // Insert sub-register copy + const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); #ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); + MachineBasicBlock::iterator dMI = MI; + DOUT << "subreg: " << *(--dMI); #endif + } DOUT << "\n"; MBB->remove(MI); @@ -149,15 +154,19 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { DOUT << "subreg: CONVERTING: " << *MI; - // Insert sub-register copy - const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg); - const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); - + if (DstSubReg == InsReg) { + // No need to insert an identify copy instruction. + DOUT << "subreg: eliminated!"; + } else { + // Insert sub-register copy + const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); #ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); + MachineBasicBlock::iterator dMI = MI; + DOUT << "subreg: " << *(--dMI); #endif + } DOUT << "\n"; MBB->remove(MI); diff --git a/test/CodeGen/X86/2008-06-16-SubregsBug.ll b/test/CodeGen/X86/2008-06-16-SubregsBug.ll new file mode 100644 index 00000000000..75513b665a0 --- /dev/null +++ b/test/CodeGen/X86/2008-06-16-SubregsBug.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep mov | count 4 + +define i16 @test(i16* %tmp179) nounwind { + %tmp180 = load i16* %tmp179, align 2 ; [#uses=2] + %tmp184 = and i16 %tmp180, -1024 ; [#uses=1] + %tmp186 = icmp eq i16 %tmp184, -32768 ; [#uses=1] + br i1 %tmp186, label %bb189, label %bb288 + +bb189: ; preds = %0 + ret i16 %tmp180 + +bb288: ; preds = %0 + ret i16 32 +}