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Combine the F2 and F3 instruction classes into one file for simplicity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16484 91177308-0d34-0410-b5e6-96231b3b80d8
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//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===//
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//
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//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the SparcV8
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//===----------------------------------------------------------------------===//
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class F2 : InstV8 { // Format 2 instructions
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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let op2 = op2Val;
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let Name = name;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
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bits<4> cond;
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bit annul = 0; // currently unused
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let cond = condVal;
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let op2 = op2Val;
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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//===----------------------------------------------------------------------===//
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// Format #3 instruction classes in the SparcV8
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//
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//===----------------------------------------------------------------------===//
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class F3 : InstV8 {
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@ -28,8 +28,7 @@ class InstV8 : Instruction { // SparcV8 instruction baseline
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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include "SparcV8InstrInfo_F2.td"
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include "SparcV8InstrInfo_F3.td"
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -1,44 +0,0 @@
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//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Format #2 instruction classes in the SparcV8
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//
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//===----------------------------------------------------------------------===//
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class F2 : InstV8 { // Format 2 instructions
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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let op2 = op2Val;
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let Name = name;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
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bits<4> cond;
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bit annul = 0; // currently unused
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let cond = condVal;
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let op2 = op2Val;
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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@ -1,14 +1,50 @@
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//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===//
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//
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//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the SparcV8
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//===----------------------------------------------------------------------===//
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class F2 : InstV8 { // Format 2 instructions
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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let op2 = op2Val;
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let Name = name;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
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bits<4> cond;
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bit annul = 0; // currently unused
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let cond = condVal;
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let op2 = op2Val;
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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//===----------------------------------------------------------------------===//
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// Format #3 instruction classes in the SparcV8
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//
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//===----------------------------------------------------------------------===//
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class F3 : InstV8 {
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@ -28,8 +28,7 @@ class InstV8 : Instruction { // SparcV8 instruction baseline
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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include "SparcV8InstrInfo_F2.td"
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include "SparcV8InstrInfo_F3.td"
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -1,44 +0,0 @@
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//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Format #2 instruction classes in the SparcV8
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//
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//===----------------------------------------------------------------------===//
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class F2 : InstV8 { // Format 2 instructions
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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let op2 = op2Val;
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let Name = name;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
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bits<4> cond;
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bit annul = 0; // currently unused
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let cond = condVal;
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let op2 = op2Val;
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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