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Inline implVisitAluOverflow by introducing a nested switch to convert the intrinsic to an nodetype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154478 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3629,17 +3629,6 @@ getF32Constant(SelectionDAG &DAG, unsigned Flt) {
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return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
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return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
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}
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}
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// implVisitAluOverflow - Lower arithmetic overflow instrinsics.
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const char *
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SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
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SDValue Op1 = getValue(I.getArgOperand(0));
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SDValue Op2 = getValue(I.getArgOperand(1));
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SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
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setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
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return 0;
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}
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/// visitExp - Lower an exp intrinsic. Handles the special sequences for
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/// visitExp - Lower an exp intrinsic. Handles the special sequences for
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/// limited-precision mode.
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/// limited-precision mode.
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void
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void
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@ -4867,6 +4856,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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case Intrinsic::convertuu: {
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case Intrinsic::convertuu: {
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ISD::CvtCode Code = ISD::CVT_INVALID;
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ISD::CvtCode Code = ISD::CVT_INVALID;
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switch (Intrinsic) {
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switch (Intrinsic) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::convertff: Code = ISD::CVT_FF; break;
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case Intrinsic::convertff: Code = ISD::CVT_FF; break;
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case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
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case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
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case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
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case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
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@ -5099,18 +5089,28 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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return 0;
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return 0;
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}
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}
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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return implVisitAluOverflow(I, ISD::UADDO);
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::sadd_with_overflow:
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return implVisitAluOverflow(I, ISD::SADDO);
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case Intrinsic::usub_with_overflow:
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case Intrinsic::usub_with_overflow:
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return implVisitAluOverflow(I, ISD::USUBO);
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::ssub_with_overflow:
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return implVisitAluOverflow(I, ISD::SSUBO);
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case Intrinsic::umul_with_overflow:
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case Intrinsic::umul_with_overflow:
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return implVisitAluOverflow(I, ISD::UMULO);
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case Intrinsic::smul_with_overflow: {
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case Intrinsic::smul_with_overflow:
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ISD::NodeType Op;
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return implVisitAluOverflow(I, ISD::SMULO);
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switch (Intrinsic) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
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case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
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case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
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case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
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case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
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case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
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}
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SDValue Op1 = getValue(I.getArgOperand(0));
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SDValue Op2 = getValue(I.getArgOperand(1));
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SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
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setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
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return 0;
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}
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case Intrinsic::prefetch: {
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case Intrinsic::prefetch: {
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SDValue Ops[5];
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SDValue Ops[5];
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unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
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unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
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@ -556,8 +556,6 @@ private:
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void visitUserOp2(const Instruction &I) {
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void visitUserOp2(const Instruction &I) {
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llvm_unreachable("UserOp2 should not exist at instruction selection time!");
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llvm_unreachable("UserOp2 should not exist at instruction selection time!");
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}
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}
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const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
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void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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