Inline implVisitAluOverflow by introducing a nested switch to convert the intrinsic to an nodetype.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-04-11 04:34:11 +00:00
parent 680363b5fd
commit c42e640dc8
2 changed files with 18 additions and 20 deletions

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@ -3629,17 +3629,6 @@ getF32Constant(SelectionDAG &DAG, unsigned Flt) {
return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
} }
// implVisitAluOverflow - Lower arithmetic overflow instrinsics.
const char *
SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1));
SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
return 0;
}
/// visitExp - Lower an exp intrinsic. Handles the special sequences for /// visitExp - Lower an exp intrinsic. Handles the special sequences for
/// limited-precision mode. /// limited-precision mode.
void void
@ -4867,6 +4856,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
case Intrinsic::convertuu: { case Intrinsic::convertuu: {
ISD::CvtCode Code = ISD::CVT_INVALID; ISD::CvtCode Code = ISD::CVT_INVALID;
switch (Intrinsic) { switch (Intrinsic) {
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
case Intrinsic::convertff: Code = ISD::CVT_FF; break; case Intrinsic::convertff: Code = ISD::CVT_FF; break;
case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
case Intrinsic::convertfui: Code = ISD::CVT_FU; break; case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
@ -5099,18 +5089,28 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
return 0; return 0;
} }
case Intrinsic::uadd_with_overflow: case Intrinsic::uadd_with_overflow:
return implVisitAluOverflow(I, ISD::UADDO);
case Intrinsic::sadd_with_overflow: case Intrinsic::sadd_with_overflow:
return implVisitAluOverflow(I, ISD::SADDO);
case Intrinsic::usub_with_overflow: case Intrinsic::usub_with_overflow:
return implVisitAluOverflow(I, ISD::USUBO);
case Intrinsic::ssub_with_overflow: case Intrinsic::ssub_with_overflow:
return implVisitAluOverflow(I, ISD::SSUBO);
case Intrinsic::umul_with_overflow: case Intrinsic::umul_with_overflow:
return implVisitAluOverflow(I, ISD::UMULO); case Intrinsic::smul_with_overflow: {
case Intrinsic::smul_with_overflow: ISD::NodeType Op;
return implVisitAluOverflow(I, ISD::SMULO); switch (Intrinsic) {
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
}
SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1));
SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
return 0;
}
case Intrinsic::prefetch: { case Intrinsic::prefetch: {
SDValue Ops[5]; SDValue Ops[5];
unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();

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@ -556,8 +556,6 @@ private:
void visitUserOp2(const Instruction &I) { void visitUserOp2(const Instruction &I) {
llvm_unreachable("UserOp2 should not exist at instruction selection time!"); llvm_unreachable("UserOp2 should not exist at instruction selection time!");
} }
const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);