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R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics
Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,7 +58,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
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setOperationAction(ISD::FPOW, MVT::f32, Custom);
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setOperationAction(ISD::ROTL, MVT::i32, Custom);
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@ -316,7 +315,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::STORE: return LowerSTORE(Op, DAG);
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case ISD::LOAD: return LowerLOAD(Op, DAG);
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case ISD::FPOW: return LowerFPOW(Op, DAG);
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case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
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case ISD::INTRINSIC_VOID: {
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SDValue Chain = Op.getOperand(0);
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@ -918,15 +916,6 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
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return DAG.getMergeValues(Ops, 2, DL);
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}
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SDValue R600TargetLowering::LowerFPOW(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue LogBase = DAG.getNode(ISD::FLOG2, DL, VT, Op.getOperand(0));
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SDValue MulLogBase = DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), LogBase);
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return DAG.getNode(ISD::FEXP2, DL, VT, MulLogBase);
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}
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/// XXX Only kernel functions are supported, so we can assume for now that
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/// every function is a kernel function, but in the future we should use
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/// separate calling conventions for kernel and non-kernel functions.
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@ -59,7 +59,6 @@ private:
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFPOW(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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@ -1141,6 +1141,7 @@ let Predicates = [isR600] in {
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def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
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defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
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def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
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def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
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def : Pat<(fsqrt R600_Reg32:$src),
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@ -1212,6 +1213,7 @@ def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
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def SIN_eg : SIN_Common<0x8D>;
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def COS_eg : COS_Common<0x8E>;
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def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
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def : SIN_PAT <SIN_eg>;
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def : COS_PAT <COS_eg>;
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def : Pat<(fsqrt R600_Reg32:$src),
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@ -1540,13 +1542,14 @@ def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
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def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
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def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
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def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
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def LOG_IEEE_ : LOG_IEEE_Common<0x83>;
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def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
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def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
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def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
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def SIN_cm : SIN_Common<0x8D>;
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def COS_cm : COS_Common<0x8E>;
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} // End isVector = 1
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def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
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def : SIN_PAT <SIN_cm>;
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def : COS_PAT <COS_cm>;
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@ -1442,8 +1442,7 @@ def : Pat <
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/********** ================== **********/
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/* llvm.AMDGPU.pow */
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/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
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def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
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def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32, VReg_32>;
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def : Pat <
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(int_AMDGPU_div VSrc_32:$src0, VSrc_32:$src1),
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