diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b7ace2ed43d..8207eacaf9b 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1108,7 +1108,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand: {
         unsigned Reg = TLI.getExceptionAddressRegister();
-        Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
+        Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
       }
       break;
     case TargetLowering::Custom:
@@ -1142,7 +1142,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand: {
         unsigned Reg = TLI.getExceptionSelectorRegister();
-        Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
+        Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
       }
       break;
     case TargetLowering::Custom:
@@ -1911,7 +1911,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
 
       SDValue Size  = Tmp2.getOperand(1);
-      SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
+      SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
       Chain = SP.getValue(1);
       unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
       unsigned StackAlign =
@@ -1920,7 +1920,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         SP = DAG.getNode(ISD::AND, dl, VT, SP,
                          DAG.getConstant(-(uint64_t)Align, VT));
       Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size);       // Value
-      Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1);     // Output chain
+      Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1);     // Output chain
 
       Tmp2 = DAG.getCALLSEQ_END(Chain,  DAG.getIntPtrConstant(0, true),
                                 DAG.getIntPtrConstant(0, true), SDValue());
@@ -2882,7 +2882,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       // Expand to CopyFromReg if the target set 
       // StackPointerRegisterToSaveRestore.
       if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
-        Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
+        Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
                                   Node->getValueType(0));
         Tmp2 = Tmp1.getValue(1);
       } else {
@@ -2914,7 +2914,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       // Expand to CopyToReg if the target set 
       // StackPointerRegisterToSaveRestore.
       if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
-        Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
+        Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
       } else {
         Result = Tmp1;
       }
@@ -4029,7 +4029,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         Result = PromoteOp(Node->getOperand(0));
         // For FP, make Op1 a i32
         
-        Result = DAG.getConvertRndSat(Op.getValueType(), Result,
+        Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
                                       DTyOp, STyOp, RndOp, SatOp, CvtCode);
         break;
       }
@@ -4593,7 +4593,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
              CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
              CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
             "can only promote integers");
-    Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
+    Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
                                   Node->getOperand(1), Node->getOperand(2),
                                   Node->getOperand(3), Node->getOperand(4),
                                   CvtCode);
@@ -4877,11 +4877,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
     Tmp1 = Node->getOperand(0);   // Get the chain.
     Tmp2 = Node->getOperand(1);   // Get the pointer.
     if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
-      Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
+      Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
       Result = TLI.LowerOperation(Tmp3, DAG);
     } else {
       const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
-      SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
+      SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
       // Increment the pointer, VAList, to the next vaarg
       Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 
                          DAG.getConstant(VT.getSizeInBits()/8,
@@ -6578,8 +6578,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
   case ISD::VAARG: {
     SDValue Ch = Node->getOperand(0);   // Legalize the chain.
     SDValue Ptr = Node->getOperand(1);  // Legalize the pointer.
-    Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
-    Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
+    Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
+    Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
 
     // Remember that we legalized the chain.
     Hi = LegalizeOp(Hi);
@@ -7744,9 +7744,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
     SDValue RndOp = Node->getOperand(3);
     SDValue SatOp = Node->getOperand(4);
 
-    Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
+    Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
                               RndOp, SatOp, CvtCode);
-    Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
+    Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
                               RndOp, SatOp, CvtCode);
     break;
   }
@@ -7892,7 +7892,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
     break;
   case ISD::CONVERT_RNDSAT: {
     SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
-    Result = DAG.getConvertRndSat(NewVT, Op0,
+    Result = DAG.getConvertRndSat(NewVT, dl, Op0,
                                   DAG.getValueType(NewVT),
                                   DAG.getValueType(Op0.getValueType()),
                                   Node->getOperand(3),
@@ -8199,7 +8199,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
     SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
     ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
 
-    Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
+    Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
                                   RndOp, SatOp, CvtCode);
     break;
   }
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index f502a947ce7..550a71f4c8f 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -262,7 +262,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
            CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
           "can only promote integers");
   MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
-  return DAG.getConvertRndSat(OutVT, N->getOperand(0),
+  return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
                               N->getOperand(1), N->getOperand(2),
                               N->getOperand(3), N->getOperand(4), CvtCode);
 }
@@ -608,7 +608,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
 
   SmallVector<SDValue, 8> Parts(NumRegs);
   for (unsigned i = 0; i < NumRegs; ++i) {
-    Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
+    Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
     Chain = Parts[i].getValue(1);
   }
 
@@ -823,7 +823,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
            CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
            "can only promote integer arguments");
   SDValue InOp = GetPromotedInteger(N->getOperand(0));
-  return DAG.getConvertRndSat(N->getValueType(0), InOp,
+  return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
                               N->getOperand(1), N->getOperand(2),
                               N->getOperand(3), N->getOperand(4), CvtCode);
 }
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 916e9c6845b..ed4a89172d1 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -209,9 +209,10 @@ void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
   MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
   SDValue Chain = N->getOperand(0);
   SDValue Ptr = N->getOperand(1);
+  DebugLoc dl = N->getDebugLoc();
 
-  Lo = DAG.getVAArg(NVT, Chain, Ptr, N->getOperand(2));
-  Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, N->getOperand(2));
+  Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
+  Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2));
 
   // Handle endianness of the load.
   if (TLI.isBigEndian())
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 8ae42ababc8..5fb9f5b409e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -126,7 +126,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
   MVT NewVT = N->getValueType(0).getVectorElementType();
   SDValue Op0 = GetScalarizedVector(N->getOperand(0));
-  return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
+  return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 
+                              Op0, DAG.getValueType(NewVT),
                               DAG.getValueType(Op0.getValueType()),
                               N->getOperand(3),
                               N->getOperand(4),
@@ -533,6 +534,7 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
                                                   SDValue &Hi) {
   MVT LoVT, HiVT;
+  DebugLoc dl = N->getDebugLoc();
   GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
   SDValue VLo, VHi;
   GetSplitVector(N->getOperand(0), VLo, VHi);
@@ -545,8 +547,10 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
   SDValue SatOp = N->getOperand(4);
   ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
 
-  Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
-  Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
+  Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, 
+                            CvtCode);
+  Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
+                            CvtCode);
 }
 
 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
@@ -1454,6 +1458,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
+  DebugLoc dl = N->getDebugLoc();
   SDValue InOp  = N->getOperand(0);
   SDValue RndOp = N->getOperand(3);
   SDValue SatOp = N->getOperand(4);
@@ -1475,7 +1480,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
     InVT = InOp.getValueType();
     InVTNumElts = InVT.getVectorNumElements();
     if (InVTNumElts == WidenNumElts)
-      return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
+      return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
                                   SatOp, CvtCode);
   }
 
@@ -1490,20 +1495,20 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
       unsigned NumConcat = WidenNumElts/InVTNumElts;
       SmallVector<SDValue, 16> Ops(NumConcat);
       Ops[0] = InOp;
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
+      SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
       for (unsigned i = 1; i != NumConcat; ++i) {
         Ops[i] = UndefVal;
       }
-      InOp = DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT, &Ops[0], NumConcat);
-      return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
+      InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
+      return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
                                   SatOp, CvtCode);
     }
 
     if (InVTNumElts % WidenNumElts == 0) {
       // Extract the input and convert the shorten input vector.
-      InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp,
+      InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
                          DAG.getIntPtrConstant(0));
-      return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
+      return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
                                 SatOp, CvtCode);
     }
   }
@@ -1517,17 +1522,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
   unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
   unsigned i;
   for (i=0; i < MinElts; ++i) {
-    SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp,
+    SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
                                  DAG.getIntPtrConstant(i));
-    Ops[i] = DAG.getConvertRndSat(WidenVT, ExtVal, DTyOp, STyOp, RndOp,
+    Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
                                         SatOp, CvtCode);
   }
 
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
+  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
   for (; i < WidenNumElts; ++i)
     Ops[i] = UndefVal;
 
-  return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
+  return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 9d480e68b5f..f8289f9f186 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -440,9 +440,11 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
             MVT VT = Arg.getValueType();
             unsigned VReg = MF.getRegInfo().
               createVirtualRegister(TLI.getRegClassFor(VT));
-            Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
+            Chain = DAG.getCopyToReg(Chain, Arg.getNode()->getDebugLoc(),
+                                     VReg, Arg, InFlag);
             InFlag = Chain.getValue(1);
-            Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
+            Arg = DAG.getCopyFromReg(Chain, Arg.getNode()->getDebugLoc(),
+                                     VReg, VT, InFlag);
             Chain = Arg.getValue(1);
             InFlag = Arg.getValue(2);
           }