From c47bd9899b639c3384268f871009259c2a94fba4 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Fri, 25 Jan 2013 21:55:32 +0000 Subject: [PATCH] Add instruction encodings / disassembly support for l4r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 49 +++++++++++++++++++ lib/Target/XCore/XCoreInstrFormats.td | 23 ++++++++- lib/Target/XCore/XCoreInstrInfo.td | 27 +++++----- test/MC/Disassembler/XCore/xcore.txt | 11 +++++ 4 files changed, 93 insertions(+), 17 deletions(-) diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 821c33da516..a94f5b9c2ac 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -180,6 +180,16 @@ static DecodeStatus DecodeL5RInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -636,6 +646,45 @@ DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td index 624036205c4..8dceb30b0da 100644 --- a/lib/Target/XCore/XCoreInstrFormats.td +++ b/lib/Target/XCore/XCoreInstrFormats.td @@ -218,8 +218,29 @@ class _F0R opc, dag outs, dag ins, string asmstr, list pattern> let Inst{4-0} = opc{4-0}; } -class _L4R pattern> +class _FL4R opc, dag outs, dag ins, string asmstr, list pattern> : InstXCore<4, outs, ins, asmstr, pattern> { + bits<4> d; + + let Inst{31-27} = opc{5-1}; + let Inst{26-21} = 0b111111; + let Inst{20} = opc{0}; + let Inst{19-16} = d; + let Inst{15-11} = 0b11111; +} + +// L4R with 4th operand as both a source and a destination. +class _FL4RSrcDst opc, dag outs, dag ins, string asmstr, + list pattern> + : _FL4R { + let DecoderMethod = "DecodeL4RSrcDstInstruction"; +} + +// L4R with 1st and 4th operand as both a source and a destination. +class _FL4RSrcDstSrcDst opc, dag outs, dag ins, string asmstr, + list pattern> + : _FL4R { + let DecoderMethod = "DecodeL4RSrcDstSrcDstInstruction"; } class _FL5R opc, dag outs, dag ins, string asmstr, list pattern> diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index b48a31d526d..770b1fc0dd5 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -463,25 +463,20 @@ def ST8_l3r : _FL3R<0b100011100, (outs), } // Four operand long -let Constraints = "$src1 = $dst1,$src2 = $dst2" in { -def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, - GRRegs:$src4), - "maccu $dst1, $dst2, $src3, $src4", - []>; +let Constraints = "$e = $a,$f = $b" in { +def MACCU_l4r : _FL4RSrcDstSrcDst< + 0b000001, (outs GRRegs:$a, GRRegs:$b), + (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; -def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, - GRRegs:$src4), - "maccs $dst1, $dst2, $src3, $src4", - []>; +def MACCS_l4r : _FL4RSrcDstSrcDst< + 0b000010, (outs GRRegs:$a, GRRegs:$b), + (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; } -let Constraints = "$src1 = $dst2" in -def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), - "crc8 $dst2, $dst1, $src2, $src3", - []>; +let Constraints = "$e = $b" in +def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), + (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), + "crc8 $b, $a, $c, $d", []>; // Five operand long diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index fdc769649d0..e1cec70f48b 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -472,3 +472,14 @@ # CHECK: lsub r1, r8, r7, r11, r5 0xcf 0xfd 0x85 0x0f + +# l4r instructions + +# CHECK: crc8 r6, r3, r4, r11 +0x73 0xfd 0xe6 0x07 + +# CHECK: maccs r11, r8, r2, r4 +0xf8 0xfa 0xe8 0x0f + +# CHECK: maccu r0, r2, r5, r8 +0x44 0xfd 0xf2 0x07