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[mips] Refactor conditional branch instructions with two register operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-20 04:10:13 +00:00
parent cef95f702a
commit c488901355
3 changed files with 22 additions and 8 deletions
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4
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -166,8 +166,8 @@ def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
/// Jump and Branch Instructions
def JR64 : IndirectBranch<CPU64Regs>;
def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>;

13
lib/Target/Mips/MipsInstrFormats.td
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@ -252,6 +252,19 @@ class SRLV_FM<bits<6> funct, bit rotate> {
let Inst{5-0} = funct;
}
class BEQ_FM<bits<6> op> {
bits<5> rs;
bits<5> rt;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-0} = offset;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

13
lib/Target/Mips/MipsInstrInfo.td
View File

@ -545,10 +545,11 @@ multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
}
// Conditional Branch
class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
!strconcat(instr_asm, "\t$rs, $rt, $imm16"),
[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
!strconcat(opstr, "\t$rs, $rt, $offset"),
[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
FrmI> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
@ -996,8 +997,8 @@ def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
Requires<[RelocStatic, HasStdEnc]>, IsBranch;
def JR : IndirectBranch<CPURegs>;
def B : UncondBranch<0x04, "b">;
def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
def BNE : CBranch<0x05, "bne", setne, CPURegs>;
def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;