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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Try to use v_madak_f32
This is a code size optimization when the constant only has one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230148 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
9036390498
commit
c490f78e53
@ -859,6 +859,84 @@ SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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static void removeModOperands(MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
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AMDGPU::OpName::src0_modifiers);
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int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
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AMDGPU::OpName::src1_modifiers);
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int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
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AMDGPU::OpName::src2_modifiers);
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MI.RemoveOperand(Src2ModIdx);
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MI.RemoveOperand(Src1ModIdx);
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MI.RemoveOperand(Src0ModIdx);
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}
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bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const {
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if (!MRI->hasOneNonDBGUse(Reg))
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return false;
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unsigned Opc = UseMI->getOpcode();
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if (Opc == AMDGPU::V_MAD_F32) {
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// Don't fold if we are using source modifiers. The new VOP2 instructions
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// don't have them.
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if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
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hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
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hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
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return false;
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}
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MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
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MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
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MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
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// The VOP2 src0 can't be an SGPR since the constant bus use will be the
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// literal constant.
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if (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))
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return false;
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// Added part is the constant: Use v_madak_f32
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if (Src2->isReg() && Src2->getReg() == Reg) {
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// Not allowed to use constant bus for another operand.
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// We can however allow an inline immediate as src0.
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if (!Src0->isImm() &&
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(Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
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return false;
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if (!Src1->isReg() ||
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(Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
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return false;
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const int64_t Imm = DefMI->getOperand(1).getImm();
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// FIXME: This would be a lot easier if we could return a new instruction
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// instead of having to modify in place.
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// Remove these first since they are at the end.
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UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
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AMDGPU::OpName::omod));
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UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
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AMDGPU::OpName::clamp));
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Src2->ChangeToImmediate(Imm);
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// These come before src2.
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removeModOperands(*UseMI);
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UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
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bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
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if (DeleteDef)
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DefMI->eraseFromParent();
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return true;
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}
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}
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return false;
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}
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bool
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SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA) const {
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@ -136,6 +136,9 @@ public:
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
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bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const final;
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bool isSALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SALU;
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}
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193
test/CodeGen/R600/madak.ll
Normal file
193
test/CodeGen/R600/madak.ll
Normal file
@ -0,0 +1,193 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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; FIXME: Enable VI
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare float @llvm.fabs.f32(float) nounwind readnone
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; GCN-LABEL: {{^}}madak_f32:
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; GCN: buffer_load_dword [[VA:v[0-9]+]]
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; GCN: buffer_load_dword [[VB:v[0-9]+]]
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; GCN: v_madak_f32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000
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define void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
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%in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %in.a.gep, align 4
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%b = load float addrspace(1)* %in.b.gep, align 4
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%mul = fmul float %a, %b
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; Make sure this is only folded with one use. This is a code size
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; optimization and if we fold the immediate multiple times, we'll undo
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; it.
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; GCN-LABEL: {{^}}madak_2_use_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], [[VK]]
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; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VC]], [[VK]]
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; GCN: s_endpgm
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define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
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%in.gep.2 = getelementptr float addrspace(1)* %in.gep.0, i32 2
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%out.gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%out.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
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%a = load float addrspace(1)* %in.gep.0, align 4
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%b = load float addrspace(1)* %in.gep.1, align 4
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%c = load float addrspace(1)* %in.gep.2, align 4
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%mul0 = fmul float %a, %b
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%mul1 = fmul float %a, %c
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%madak0 = fadd float %mul0, 10.0
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%madak1 = fadd float %mul1, 10.0
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store float %madak0, float addrspace(1)* %out.gep.0, align 4
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store float %madak1, float addrspace(1)* %out.gep.1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}madak_m_inline_imm_f32:
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; GCN: buffer_load_dword [[VA:v[0-9]+]]
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; GCN: v_madak_f32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
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define void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %in.a.gep, align 4
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%mul = fmul float 4.0, %a
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; Make sure nothing weird happens with a value that is also allowed as
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; an inline immediate.
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; GCN-LABEL: {{^}}madak_inline_imm_f32:
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; GCN: buffer_load_dword [[VA:v[0-9]+]]
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; GCN: buffer_load_dword [[VB:v[0-9]+]]
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; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0
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define void @madak_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
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%in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %in.a.gep, align 4
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%b = load float addrspace(1)* %in.b.gep, align 4
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%mul = fmul float %a, %b
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%madak = fadd float %mul, 4.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; We can't use an SGPR when forming madak
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; GCN-LABEL: {{^}}s_v_madak_f32:
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; GCN: s_load_dword [[SB:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
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; GCN-NOT: v_madak_f32
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; GCN: v_mad_f32 {{v[0-9]+}}, [[SB]], [[VA]], [[VK]]
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define void @s_v_madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float %b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %in.a.gep, align 4
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%mul = fmul float %a, %b
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: @v_s_madak_f32
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; GCN-DAG: s_load_dword [[SB:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
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; GCN-NOT: v_madak_f32
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; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[SB]], [[VK]]
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define void @v_s_madak_f32(float addrspace(1)* noalias %out, float %a, float addrspace(1)* noalias %in.b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%b = load float addrspace(1)* %in.b.gep, align 4
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%mul = fmul float %a, %b
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_s_madak_f32:
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; GCN-NOT: v_madak_f32
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; GCN: v_mad_f32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @s_s_madak_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
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%mul = fmul float %a, %b
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_madak_src0_modifier_f32:
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; GCN: buffer_load_dword [[VA:v[0-9]+]]
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; GCN: buffer_load_dword [[VB:v[0-9]+]]
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; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}}
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; GCN: s_endpgm
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define void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
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%in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %in.a.gep, align 4
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%b = load float addrspace(1)* %in.b.gep, align 4
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%a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
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%mul = fmul float %a.fabs, %b
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_madak_src1_modifier_f32:
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; GCN: buffer_load_dword [[VA:v[0-9]+]]
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; GCN: buffer_load_dword [[VB:v[0-9]+]]
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; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}}
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; GCN: s_endpgm
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define void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
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%in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %in.a.gep, align 4
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%b = load float addrspace(1)* %in.b.gep, align 4
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%b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
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%mul = fmul float %a, %b.fabs
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%madak = fadd float %mul, 10.0
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store float %madak, float addrspace(1)* %out.gep, align 4
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ret void
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}
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