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Clean up sub-register implementation by moving subReg information back to

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MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44104 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-11-14 07:59:08 +00:00
parent f9572a4c2b
commit c498b0281f
9 changed files with 53 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
include/llvm/CodeGen/MachineInstr.h
View File

@@ -76,6 +76,10 @@ private:
/// offset - Offset to address of global or external, only valid for
/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
int offset;
/// subReg - SubRegister number, only valid for MO_Register. A value of 0
/// indicates the MO_Register has no subReg.
unsigned subReg;
} auxInfo;
MachineOperand() {}
@@ -182,6 +186,10 @@ public:
"Wrong MachineOperand accessor");
return auxInfo.offset;
}
unsigned getSubReg() const {
assert(isRegister() && "Wrong MachineOperand accessor");
return auxInfo.subReg;
}
const char *getSymbolName() const {
assert(isExternalSymbol() && "Wrong MachineOperand accessor");
return contents.SymbolName;
@@ -267,6 +275,10 @@ public:
"Wrong MachineOperand accessor");
auxInfo.offset = Offset;
}
void setSubReg(unsigned subReg) {
assert(isRegister() && "Wrong MachineOperand accessor");
auxInfo.subReg = subReg;
}
void setConstantPoolIndex(unsigned Idx) {
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
contents.immedVal = Idx;
@@ -451,7 +463,8 @@ public:
/// addRegOperand - Add a register operand.
///
void addRegOperand(unsigned Reg, bool IsDef, bool IsImp = false,
bool IsKill = false, bool IsDead = false) {
bool IsKill = false, bool IsDead = false,
unsigned SubReg = 0) {
MachineOperand &Op = AddNewOperand(IsImp);
Op.opType = MachineOperand::MO_Register;
Op.IsDef = IsDef;
@@ -459,6 +472,7 @@ public:
Op.IsKill = IsKill;
Op.IsDead = IsDead;
Op.contents.RegNo = Reg;
Op.auxInfo.subReg = SubReg;
}
/// addImmOperand - Add a zero extended constant argument to the

4
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@@ -39,8 +39,8 @@ public:
const
MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false,
bool isImp = false, bool isKill = false,
bool isDead = false) const {
MI->addRegOperand(RegNo, isDef, isImp, isKill, isDead);
bool isDead = false, unsigned SubReg = 0) const {
MI->addRegOperand(RegNo, isDef, isImp, isKill, isDead, SubReg);
return *this;
}

19
include/llvm/CodeGen/SSARegMap.h
View File

@@ -26,7 +26,6 @@ class TargetRegisterClass;
class SSARegMap {
IndexedMap<const TargetRegisterClass*, VirtReg2IndexFunctor> RegClassMap;
IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegSubIdxMap;
unsigned NextRegNum;
public:
@@ -43,30 +42,12 @@ class SSARegMap {
assert(RegClass && "Cannot create register without RegClass!");
RegClassMap.grow(NextRegNum);
RegClassMap[NextRegNum] = RegClass;
RegSubIdxMap.grow(NextRegNum);
RegSubIdxMap[NextRegNum] = std::make_pair(0,0);
return NextRegNum++;
}
unsigned getLastVirtReg() const {
return NextRegNum - 1;
}
void setIsSubRegister(unsigned Reg, unsigned SuperReg, unsigned SubIdx) {
RegSubIdxMap[Reg] = std::make_pair(SuperReg, SubIdx);
}
bool isSubRegister(unsigned Reg) const {
return RegSubIdxMap[Reg].first != 0;
}
unsigned getSuperRegister(unsigned Reg) const {
return RegSubIdxMap[Reg].first;
}
unsigned getSubRegisterIndex(unsigned Reg) const {
return RegSubIdxMap[Reg].second;
}
};
} // End llvm namespace