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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jia Liu 2012-02-27 02:21:34 +00:00
parent 23b6ec906a
commit c4a238c20f
1 changed files with 14 additions and 16 deletions
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30
lib/Target/Mips/MipsRegisterInfo.td
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@ -1,4 +1,4 @@
//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -69,8 +69,6 @@ class HWR<bits<5> num, string n> : MipsReg<n> {
//===----------------------------------------------------------------------===//
let Namespace = "Mips" in {
// FIXME: Fix DwarfRegNum.
// General Purpose Registers
def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
@ -116,19 +114,19 @@ let Namespace = "Mips" in {
def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;