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Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-11-10 02:13:22 +00:00
parent 201ab3acff
commit c4bb67c8d9
2 changed files with 12 additions and 8 deletions
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3
lib/Target/Mips/Mips.td
View File

@ -59,7 +59,8 @@ def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips2 ISA Support">;
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support", [FeatureCondMov]>;
"Mips32 ISA Support",
[FeatureCondMov, FeatureBitCount]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg]>;

17
lib/Target/Mips/MipsInstrInfo.td
View File

@ -281,10 +281,13 @@ class EffectiveAddress<string instr_asm> :
instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
// Count Leading Ones/Zeros in Word
class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
!strconcat(instr_asm, "\t$dst, $src"),
[(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
Requires<[HasBitCount]> {
let shamt = 0;
let rt = rd;
}
// Sign Extend in Register.
class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
@ -446,10 +449,10 @@ let Predicates = [HasSEInReg] in {
}
/// Count Leading
let Predicates = [HasBitCount] in {
let rt = 0 in
def CLZ : CountLeading<0b010110, "clz", ctlz>;
}
def CLZ : CountLeading<0b100000, "clz",
[(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
def CLO : CountLeading<0b100001, "clo",
[(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
/// Byte Swap
let Predicates = [HasSwap] in {