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[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.

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Summary:
This is because the FP64A the hardware will redirect 32-bit reads/writes
from/to odd-numbered registers to the upper 32-bits of the corresponding
even register. In effect, simulating FR=0 mode when FR=0 mode is not
available.

Unfortunately, we have to make the decision to avoid mfc1/mtc1 before
register allocation so we currently do this for even registers too.

FPXX has a similar requirement on 32-bit architectures that lack
mfhc1/mthc1 so this patch also handles the affected moves from the FPU for
FPXX too. Moves to the FPU were supported by an earlier commit.

Differential Revision: http://reviews.llvm.org/D4484


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-07-14 13:08:14 +00:00
parent 543f70b040
commit c4ce78e261
7 changed files with 443 additions and 71 deletions
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10
lib/Target/Mips/MipsMachineFunction.cpp
View File

@ -137,12 +137,12 @@ MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *Val) {
return MachinePointerInfo(E);
}
int MipsFunctionInfo::getBuildPairF64_FI(const TargetRegisterClass *RC) {
if (BuildPairF64_FI == -1) {
BuildPairF64_FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
RC->getAlignment(), false);
int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
if (MoveF64ViaSpillFI == -1) {
MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject(
RC->getSize(), RC->getAlignment(), false);
}
return BuildPairF64_FI;
return MoveF64ViaSpillFI;
}
void MipsFunctionInfo::anchor() { }