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Port some bugfixes in shift handling from SimplifyDemandedBits over to
ComputeMaskedBits. DemandedMasks and KnownZero/One masks should never have bits set out of the range of the base datatype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28768 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -442,10 +442,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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unsigned ShAmt = SA->getValue();
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// Compute the new bits that are at the top now.
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uint64_t HighBits = (1ULL << ShAmt)-1;
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HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
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uint64_t TypeMask = MVT::getIntVTBitMask(VT);
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if (SimplifyDemandedBits(Op.getOperand(0),
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(DemandedMask << ShAmt) & TypeMask,
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KnownZero, KnownOne, TLO, Depth+1))
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@ -455,7 +452,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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KnownOne &= TypeMask;
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KnownZero >>= ShAmt;
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KnownOne >>= ShAmt;
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KnownZero |= HighBits; // high bits known zero.
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uint64_t HighBits = (1ULL << ShAmt)-1;
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HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
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KnownZero |= HighBits; // High bits known zero.
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}
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break;
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case ISD::SRA:
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@ -464,14 +464,14 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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unsigned ShAmt = SA->getValue();
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// Compute the new bits that are at the top now.
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uint64_t HighBits = (1ULL << ShAmt)-1;
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HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
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uint64_t TypeMask = MVT::getIntVTBitMask(VT);
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uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
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// If any of the demanded bits are produced by the sign extension, we also
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// demand the input sign bit.
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uint64_t HighBits = (1ULL << ShAmt)-1;
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HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
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if (HighBits & DemandedMask)
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InDemandedMask |= MVT::getIntVTSignBit(VT);
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@ -481,12 +481,12 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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KnownZero &= TypeMask;
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KnownOne &= TypeMask;
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KnownZero >>= SA->getValue();
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KnownOne >>= SA->getValue();
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KnownZero >>= ShAmt;
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KnownOne >>= ShAmt;
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// Handle the sign bits.
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
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SignBit >>= ShAmt; // Adjust to where it is now in the mask.
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// If the input sign bit is known to be zero, or if none of the top bits
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// are demanded, turn this into an unsigned shift right.
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@ -780,50 +780,66 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
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case ISD::SHL:
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// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
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if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t LowBits = (1ULL << SA->getValue())-1;
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Mask >>= SA->getValue();
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ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
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ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(),
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KnownZero, KnownOne, Depth+1);
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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KnownZero <<= SA->getValue();
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KnownOne <<= SA->getValue();
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KnownZero |= LowBits; // low bits known zero
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KnownOne &= ~LowBits; // and known not to be one.
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KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
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}
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return;
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
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if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t HighBits = (1ULL << SA->getValue())-1;
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HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
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Mask <<= SA->getValue();
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ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
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MVT::ValueType VT = Op.getValueType();
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unsigned ShAmt = SA->getValue();
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uint64_t TypeMask = MVT::getIntVTBitMask(VT);
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ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask,
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KnownZero, KnownOne, Depth+1);
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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KnownZero >>= SA->getValue();
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KnownOne >>= SA->getValue();
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KnownZero |= HighBits; // high bits known zero
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KnownOne &= ~HighBits; // and known not to be one.
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KnownZero &= TypeMask;
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KnownOne &= TypeMask;
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KnownZero >>= ShAmt;
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KnownOne >>= ShAmt;
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uint64_t HighBits = (1ULL << ShAmt)-1;
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HighBits <<= MVT::getSizeInBits(VT)-ShAmt;
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KnownZero |= HighBits; // High bits known zero.
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}
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return;
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case ISD::SRA:
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if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t HighBits = (1ULL << SA->getValue())-1;
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HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
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Mask <<= SA->getValue();
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ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
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assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
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KnownZero >>= SA->getValue();
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KnownOne >>= SA->getValue();
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MVT::ValueType VT = Op.getValueType();
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unsigned ShAmt = SA->getValue();
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// Compute the new bits that are at the top now.
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uint64_t TypeMask = MVT::getIntVTBitMask(VT);
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uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask;
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// If any of the demanded bits are produced by the sign extension, we also
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// demand the input sign bit.
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uint64_t HighBits = (1ULL << ShAmt)-1;
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HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
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if (HighBits & Mask)
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InDemandedMask |= MVT::getIntVTSignBit(VT);
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ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
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Depth+1);
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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KnownZero &= TypeMask;
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KnownOne &= TypeMask;
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KnownZero >>= ShAmt;
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KnownOne >>= ShAmt;
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// Handle the sign bits.
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
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SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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SignBit >>= ShAmt; // Adjust to where it is now in the mask.
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if (KnownZero & SignBit) {
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KnownZero |= HighBits; // New bits are known zero
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KnownOne &= ~HighBits; // and known not to be one.
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KnownZero |= HighBits; // New bits are known zero.
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} else if (KnownOne & SignBit) {
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KnownOne |= HighBits; // New bits are known one
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KnownZero &= ~HighBits; // and known not to be zero.
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KnownOne |= HighBits; // New bits are known one.
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}
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}
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return;
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