mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-05 09:24:28 +00:00
Fixed bug in searchPath function for finding nodes between two recurrences.
Changed dependence analyzer to only use dep distances of 2 or less. This is experimental. Changed MSchedGraph to be able to represent more then one BB (first steps). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21641 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner
@ -153,13 +153,13 @@ MSchedGraph::MSchedGraph(const MachineBasicBlock *bb,
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std::map<const MachineInstr*, unsigned> &ignoreInstrs,
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DependenceAnalyzer &DA,
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std::map<MachineInstr*, Instruction*> &machineTollvm)
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: BB(bb), Target(targ) {
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: Target(targ) {
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//Make sure BB is not null,
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assert(BB != NULL && "Basic Block is null");
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//DEBUG(std::cerr << "Constructing graph for " << bb << "\n");
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assert(bb != NULL && "Basic Block is null");
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BBs.push_back(bb);
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//Create nodes and edges for this BB
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buildNodesAndEdges(ignoreInstrs, DA, machineTollvm);
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@ -170,7 +170,9 @@ MSchedGraph::MSchedGraph(const MachineBasicBlock *bb,
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//Copies the graph and keeps a map from old to new nodes
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MSchedGraph::MSchedGraph(const MSchedGraph &G,
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std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
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: BB(G.BB), Target(G.Target) {
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: Target(G.Target) {
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BBs = G.BBs;
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std::map<MSchedGraphNode*, MSchedGraphNode*> oldToNew;
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//Copy all nodes
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@ -336,179 +338,184 @@ void MSchedGraph::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ig
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std::vector<const MachineInstr*> phiInstrs;
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unsigned index = 0;
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//Loop over instructions in MBB and add nodes and edges
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for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
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MI != e; ++MI) {
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for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
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BE = BBs.end(); B != BE; ++B) {
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const MachineBasicBlock *BB = *B;
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//Ignore indvar instructions
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if(ignoreInstrs.count(MI)) {
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++index;
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continue;
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}
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//Get each instruction of machine basic block, get the delay
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//using the op code, create a new node for it, and add to the
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//graph.
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MachineOpCode opCode = MI->getOpcode();
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int delay;
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#if 0 // FIXME: LOOK INTO THIS
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//Check if subsequent instructions can be issued before
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//the result is ready, if so use min delay.
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if(MTI->hasResultInterlock(MIopCode))
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delay = MTI->minLatency(MIopCode);
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else
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#endif
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//Get delay
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delay = MTI->maxLatency(opCode);
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//Create new node for this machine instruction and add to the graph.
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//Create only if not a nop
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if(MTI->isNop(opCode))
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continue;
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//Sparc BE does not use PHI opcode, so assert on this case
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assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
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bool isBranch = false;
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//We want to flag the branch node to treat it special
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if(MTI->isBranch(opCode))
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isBranch = true;
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//Node is created and added to the graph automatically
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MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
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isBranch);
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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//Check OpCode to keep track of memory operations to add memory
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//dependencies later.
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if(MTI->isLoad(opCode) || MTI->isStore(opCode))
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memInstructions.push_back(node);
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//Loop over all operands, and put them into the register number to
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//graph node map for determining dependencies
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//If an operands is a use/def, we have an anti dependence to itself
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for(unsigned i=0; i < MI->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = MI->getOperand(i);
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//Check if it has an allocated register
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if(mOp.hasAllocatedReg()) {
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int regNum = mOp.getReg();
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if(regNum != SparcV9::g0) {
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//Put into our map
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regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
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}
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//Loop over instructions in MBB and add nodes and edges
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for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
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MI != e; ++MI) {
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//Ignore indvar instructions
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if(ignoreInstrs.count(MI)) {
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++index;
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continue;
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}
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//Add virtual registers dependencies
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//Check if any exist in the value map already and create dependencies
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//between them.
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if(mOp.getType() == MachineOperand::MO_VirtualRegister
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|| mOp.getType() == MachineOperand::MO_CCRegister) {
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//Make sure virtual register value is not null
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assert((mOp.getVRegValue() != NULL) && "Null value is defined");
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//Check if this is a read operation in a phi node, if so DO NOT PROCESS
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if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
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DEBUG(std::cerr << "Read Operation in a PHI node\n");
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//Get each instruction of machine basic block, get the delay
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//using the op code, create a new node for it, and add to the
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//graph.
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MachineOpCode opCode = MI->getOpcode();
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int delay;
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#if 0 // FIXME: LOOK INTO THIS
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//Check if subsequent instructions can be issued before
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//the result is ready, if so use min delay.
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if(MTI->hasResultInterlock(MIopCode))
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delay = MTI->minLatency(MIopCode);
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else
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#endif
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//Get delay
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delay = MTI->maxLatency(opCode);
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//Create new node for this machine instruction and add to the graph.
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//Create only if not a nop
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if(MTI->isNop(opCode))
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continue;
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//Sparc BE does not use PHI opcode, so assert on this case
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assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
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bool isBranch = false;
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//We want to flag the branch node to treat it special
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if(MTI->isBranch(opCode))
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isBranch = true;
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//Node is created and added to the graph automatically
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MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
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isBranch);
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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//Check OpCode to keep track of memory operations to add memory
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//dependencies later.
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if(MTI->isLoad(opCode) || MTI->isStore(opCode))
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memInstructions.push_back(node);
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//Loop over all operands, and put them into the register number to
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//graph node map for determining dependencies
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//If an operands is a use/def, we have an anti dependence to itself
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for(unsigned i=0; i < MI->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = MI->getOperand(i);
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//Check if it has an allocated register
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if(mOp.hasAllocatedReg()) {
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int regNum = mOp.getReg();
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if(regNum != SparcV9::g0) {
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//Put into our map
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regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
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}
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continue;
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}
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if (const Value* srcI = mOp.getVRegValue()) {
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//Find value in the map
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std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
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= valuetoNodeMap.find(srcI);
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//If there is something in the map already, add edges from
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//those instructions
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//to this one we are processing
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if(V != valuetoNodeMap.end()) {
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addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
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//Add to value map
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V->second.push_back(std::make_pair(i,node));
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//Add virtual registers dependencies
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//Check if any exist in the value map already and create dependencies
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//between them.
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if(mOp.getType() == MachineOperand::MO_VirtualRegister
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|| mOp.getType() == MachineOperand::MO_CCRegister) {
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//Make sure virtual register value is not null
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assert((mOp.getVRegValue() != NULL) && "Null value is defined");
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//Check if this is a read operation in a phi node, if so DO NOT PROCESS
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if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
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DEBUG(std::cerr << "Read Operation in a PHI node\n");
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continue;
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}
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if (const Value* srcI = mOp.getVRegValue()) {
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//Find value in the map
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std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
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= valuetoNodeMap.find(srcI);
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//If there is something in the map already, add edges from
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//those instructions
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//to this one we are processing
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if(V != valuetoNodeMap.end()) {
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addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
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//Add to value map
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V->second.push_back(std::make_pair(i,node));
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}
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//Otherwise put it in the map
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else
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//Put into value map
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valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
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}
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//Otherwise put it in the map
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else
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//Put into value map
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valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
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}
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}
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++index;
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}
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++index;
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}
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//Loop over LLVM BB, examine phi instructions, and add them to our
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//phiInstr list to process
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const BasicBlock *llvm_bb = BB->getBasicBlock();
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for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
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I != E; ++I) {
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if(const PHINode *PN = dyn_cast<PHINode>(I)) {
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
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for (unsigned j = 0; j < tempMvec.size(); j++) {
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if(!ignoreInstrs.count(tempMvec[j])) {
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DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
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phiInstrs.push_back((MachineInstr*) tempMvec[j]);
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}
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}
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//Loop over LLVM BB, examine phi instructions, and add them to our
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//phiInstr list to process
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const BasicBlock *llvm_bb = BB->getBasicBlock();
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for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
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I != E; ++I) {
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if(const PHINode *PN = dyn_cast<PHINode>(I)) {
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
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for (unsigned j = 0; j < tempMvec.size(); j++) {
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if(!ignoreInstrs.count(tempMvec[j])) {
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DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
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phiInstrs.push_back((MachineInstr*) tempMvec[j]);
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}
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}
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}
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}
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}
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addMemEdges(memInstructions, DA, machineTollvm);
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addMachRegEdges(regNumtoNodeMap);
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//Finally deal with PHI Nodes and Value*
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for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
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E = phiInstrs.end(); I != E; ++I) {
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//Get Node for this instruction
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std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
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X = find(*I);
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if(X == GraphMap.end())
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continue;
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MSchedGraphNode *node = X->second;
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DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
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//Loop over operands for this instruction and add value edges
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for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = (*I)->getOperand(i);
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if((mOp.getType() == MachineOperand::MO_VirtualRegister
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|| mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
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//find the value in the map
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if (const Value* srcI = mOp.getVRegValue()) {
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//Find value in the map
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std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
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addMemEdges(memInstructions, DA, machineTollvm);
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addMachRegEdges(regNumtoNodeMap);
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//Finally deal with PHI Nodes and Value*
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for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
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E = phiInstrs.end(); I != E; ++I) {
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//Get Node for this instruction
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std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
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X = find(*I);
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if(X == GraphMap.end())
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continue;
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MSchedGraphNode *node = X->second;
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DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
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//Loop over operands for this instruction and add value edges
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for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = (*I)->getOperand(i);
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if((mOp.getType() == MachineOperand::MO_VirtualRegister
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|| mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
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//find the value in the map
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if (const Value* srcI = mOp.getVRegValue()) {
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//Find value in the map
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std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
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= valuetoNodeMap.find(srcI);
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//If there is something in the map already, add edges from
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//those instructions
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//to this one we are processing
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if(V != valuetoNodeMap.end()) {
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addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
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phiInstrs, 1);
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//If there is something in the map already, add edges from
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//those instructions
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//to this one we are processing
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if(V != valuetoNodeMap.end()) {
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addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
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phiInstrs, 1);
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}
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}
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}
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}
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}
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}
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}
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//Add dependencies for Value*s
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void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
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MSchedGraphNode *destNode, bool nodeIsUse,
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