optimize FastISel::UpdateValueMap to avoid duplicate map lookups,

and make it return the assigned register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-04-12 07:45:01 +00:00
parent a9a42259ed
commit c5040ab606
2 changed files with 13 additions and 8 deletions

View File

@ -279,7 +279,7 @@ protected:
/// the CFG.
void FastEmitBranch(MachineBasicBlock *MBB);
void UpdateValueMap(Value* I, unsigned Reg);
unsigned UpdateValueMap(Value* I, unsigned Reg);
unsigned createResultReg(const TargetRegisterClass *RC);

View File

@ -149,16 +149,21 @@ unsigned FastISel::lookUpRegForValue(Value *V) {
/// NOTE: This is only necessary because we might select a block that uses
/// a value before we select the block that defines the value. It might be
/// possible to fix this by selecting blocks in reverse postorder.
void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
if (!isa<Instruction>(I)) {
LocalValueMap[I] = Reg;
return;
return Reg;
}
if (!ValueMap.count(I))
ValueMap[I] = Reg;
else
TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
unsigned &AssignedReg = ValueMap[I];
if (AssignedReg == 0)
AssignedReg = Reg;
else {
const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
Reg, RegClass, RegClass);
}
return AssignedReg;
}
unsigned FastISel::getRegForGEPIndex(Value *Idx) {