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[mips][msa] Removed fcge, fcgt, fsge, fsgt

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These instructions were present in a draft spec but were removed before
publication.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2013-08-20 09:41:47 +00:00
parent 0371d01fb9
commit c5158b869b
3 changed files with 0 additions and 240 deletions
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20
include/llvm/IR/IntrinsicsMips.td
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@ -814,16 +814,6 @@ def int_mips_fclass_w : GCCBuiltin<"__builtin_msa_fclass_w">,
def int_mips_fclass_d : GCCBuiltin<"__builtin_msa_fclass_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], []>;
def int_mips_fcge_w : GCCBuiltin<"__builtin_msa_fcge_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fcge_d : GCCBuiltin<"__builtin_msa_fcge_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
def int_mips_fcgt_w : GCCBuiltin<"__builtin_msa_fcgt_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fcgt_d : GCCBuiltin<"__builtin_msa_fcgt_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
def int_mips_fcne_w : GCCBuiltin<"__builtin_msa_fcne_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fcne_d : GCCBuiltin<"__builtin_msa_fcne_d">,
@ -956,16 +946,6 @@ def int_mips_fslt_w : GCCBuiltin<"__builtin_msa_fslt_w">,
def int_mips_fslt_d : GCCBuiltin<"__builtin_msa_fslt_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
def int_mips_fsge_w : GCCBuiltin<"__builtin_msa_fsge_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fsge_d : GCCBuiltin<"__builtin_msa_fsge_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
def int_mips_fsgt_w : GCCBuiltin<"__builtin_msa_fsgt_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fsgt_d : GCCBuiltin<"__builtin_msa_fsgt_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
def int_mips_fsne_w : GCCBuiltin<"__builtin_msa_fsne_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fsne_d : GCCBuiltin<"__builtin_msa_fsne_d">,

44
lib/Target/Mips/MipsMSAInstrInfo.td
View File

@ -261,12 +261,6 @@ class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
class FCGE_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
class FCGE_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
class FCGT_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
class FCGT_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
@ -349,12 +343,6 @@ class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
class FSGE_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
class FSGE_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
class FSGT_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
class FSGT_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
@ -1264,16 +1252,6 @@ class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", int_mips_fceq_d,
NoItinerary, MSA128, MSA128>,
IsCommutable;
class FCGE_W_DESC : MSA_3RF_DESC_BASE<"fcge.w", int_mips_fcge_w,
NoItinerary, MSA128, MSA128>;
class FCGE_D_DESC : MSA_3RF_DESC_BASE<"fcge.d", int_mips_fcge_d,
NoItinerary, MSA128, MSA128>;
class FCGT_W_DESC : MSA_3RF_DESC_BASE<"fcgt.w", int_mips_fcgt_w,
NoItinerary, MSA128, MSA128>;
class FCGT_D_DESC : MSA_3RF_DESC_BASE<"fcgt.d", int_mips_fcgt_d,
NoItinerary, MSA128, MSA128>;
class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
NoItinerary, MSA128, MSA128>;
class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
@ -1415,16 +1393,6 @@ class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w,
class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d,
NoItinerary, MSA128, MSA128>;
class FSGE_W_DESC : MSA_3RF_DESC_BASE<"fsge.w", int_mips_fsge_w,
NoItinerary, MSA128, MSA128>;
class FSGE_D_DESC : MSA_3RF_DESC_BASE<"fsge.d", int_mips_fsge_d,
NoItinerary, MSA128, MSA128>;
class FSGT_W_DESC : MSA_3RF_DESC_BASE<"fsgt.w", int_mips_fsgt_w,
NoItinerary, MSA128, MSA128>;
class FSGT_D_DESC : MSA_3RF_DESC_BASE<"fsgt.d", int_mips_fsgt_d,
NoItinerary, MSA128, MSA128>;
class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w,
NoItinerary, MSA128, MSA128>;
class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d,
@ -2198,12 +2166,6 @@ def FCLT_D : FCLT_D_ENC, FCLT_D_DESC, Requires<[HasMSA]>;
def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC, Requires<[HasMSA]>;
def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC, Requires<[HasMSA]>;
def FCGE_W : FCGE_W_ENC, FCGE_W_DESC, Requires<[HasMSA]>;
def FCGE_D : FCGE_D_ENC, FCGE_D_DESC, Requires<[HasMSA]>;
def FCGT_W : FCGT_W_ENC, FCGT_W_DESC, Requires<[HasMSA]>;
def FCGT_D : FCGT_D_ENC, FCGT_D_DESC, Requires<[HasMSA]>;
def FCNE_W : FCNE_W_ENC, FCNE_W_DESC, Requires<[HasMSA]>;
def FCNE_D : FCNE_D_ENC, FCNE_D_DESC, Requires<[HasMSA]>;
@ -2283,12 +2245,6 @@ def FSLE_D : FSLE_D_ENC, FSLE_D_DESC, Requires<[HasMSA]>;
def FSLT_W : FSLT_W_ENC, FSLT_W_DESC, Requires<[HasMSA]>;
def FSLT_D : FSLT_D_ENC, FSLT_D_DESC, Requires<[HasMSA]>;
def FSGE_W : FSGE_W_ENC, FSGE_W_DESC, Requires<[HasMSA]>;
def FSGE_D : FSGE_D_ENC, FSGE_D_DESC, Requires<[HasMSA]>;
def FSGT_W : FSGT_W_ENC, FSGT_W_DESC, Requires<[HasMSA]>;
def FSGT_D : FSGT_D_ENC, FSGT_D_DESC, Requires<[HasMSA]>;
def FSNE_W : FSNE_W_ENC, FSNE_W_DESC, Requires<[HasMSA]>;
def FSNE_D : FSNE_D_ENC, FSNE_D_DESC, Requires<[HasMSA]>;

176
test/CodeGen/Mips/msa/3rf_int_float.ll
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@ -44,94 +44,6 @@ declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind
; CHECK: st.d
; CHECK: .size llvm_mips_fceq_d_test
;
@llvm_mips_fcge_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcge_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fcge_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_fcge_w_test() nounwind {
entry:
%0 = load <4 x float>* @llvm_mips_fcge_w_ARG1
%1 = load <4 x float>* @llvm_mips_fcge_w_ARG2
%2 = tail call <4 x i32> @llvm.mips.fcge.w(<4 x float> %0, <4 x float> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_fcge_w_RES
ret void
}
declare <4 x i32> @llvm.mips.fcge.w(<4 x float>, <4 x float>) nounwind
; CHECK: llvm_mips_fcge_w_test:
; CHECK: ld.w
; CHECK: ld.w
; CHECK: fcge.w
; CHECK: st.w
; CHECK: .size llvm_mips_fcge_w_test
;
@llvm_mips_fcge_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@llvm_mips_fcge_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
@llvm_mips_fcge_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_fcge_d_test() nounwind {
entry:
%0 = load <2 x double>* @llvm_mips_fcge_d_ARG1
%1 = load <2 x double>* @llvm_mips_fcge_d_ARG2
%2 = tail call <2 x i64> @llvm.mips.fcge.d(<2 x double> %0, <2 x double> %1)
store <2 x i64> %2, <2 x i64>* @llvm_mips_fcge_d_RES
ret void
}
declare <2 x i64> @llvm.mips.fcge.d(<2 x double>, <2 x double>) nounwind
; CHECK: llvm_mips_fcge_d_test:
; CHECK: ld.d
; CHECK: ld.d
; CHECK: fcge.d
; CHECK: st.d
; CHECK: .size llvm_mips_fcge_d_test
;
@llvm_mips_fcgt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcgt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fcgt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_fcgt_w_test() nounwind {
entry:
%0 = load <4 x float>* @llvm_mips_fcgt_w_ARG1
%1 = load <4 x float>* @llvm_mips_fcgt_w_ARG2
%2 = tail call <4 x i32> @llvm.mips.fcgt.w(<4 x float> %0, <4 x float> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_fcgt_w_RES
ret void
}
declare <4 x i32> @llvm.mips.fcgt.w(<4 x float>, <4 x float>) nounwind
; CHECK: llvm_mips_fcgt_w_test:
; CHECK: ld.w
; CHECK: ld.w
; CHECK: fcgt.w
; CHECK: st.w
; CHECK: .size llvm_mips_fcgt_w_test
;
@llvm_mips_fcgt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@llvm_mips_fcgt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
@llvm_mips_fcgt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_fcgt_d_test() nounwind {
entry:
%0 = load <2 x double>* @llvm_mips_fcgt_d_ARG1
%1 = load <2 x double>* @llvm_mips_fcgt_d_ARG2
%2 = tail call <2 x i64> @llvm.mips.fcgt.d(<2 x double> %0, <2 x double> %1)
store <2 x i64> %2, <2 x i64>* @llvm_mips_fcgt_d_RES
ret void
}
declare <2 x i64> @llvm.mips.fcgt.d(<2 x double>, <2 x double>) nounwind
; CHECK: llvm_mips_fcgt_d_test:
; CHECK: ld.d
; CHECK: ld.d
; CHECK: fcgt.d
; CHECK: st.d
; CHECK: .size llvm_mips_fcgt_d_test
;
@llvm_mips_fcle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fcle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@ -352,94 +264,6 @@ declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind
; CHECK: st.d
; CHECK: .size llvm_mips_fseq_d_test
;
@llvm_mips_fsge_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fsge_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fsge_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_fsge_w_test() nounwind {
entry:
%0 = load <4 x float>* @llvm_mips_fsge_w_ARG1
%1 = load <4 x float>* @llvm_mips_fsge_w_ARG2
%2 = tail call <4 x i32> @llvm.mips.fsge.w(<4 x float> %0, <4 x float> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_fsge_w_RES
ret void
}
declare <4 x i32> @llvm.mips.fsge.w(<4 x float>, <4 x float>) nounwind
; CHECK: llvm_mips_fsge_w_test:
; CHECK: ld.w
; CHECK: ld.w
; CHECK: fsge.w
; CHECK: st.w
; CHECK: .size llvm_mips_fsge_w_test
;
@llvm_mips_fsge_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@llvm_mips_fsge_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
@llvm_mips_fsge_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_fsge_d_test() nounwind {
entry:
%0 = load <2 x double>* @llvm_mips_fsge_d_ARG1
%1 = load <2 x double>* @llvm_mips_fsge_d_ARG2
%2 = tail call <2 x i64> @llvm.mips.fsge.d(<2 x double> %0, <2 x double> %1)
store <2 x i64> %2, <2 x i64>* @llvm_mips_fsge_d_RES
ret void
}
declare <2 x i64> @llvm.mips.fsge.d(<2 x double>, <2 x double>) nounwind
; CHECK: llvm_mips_fsge_d_test:
; CHECK: ld.d
; CHECK: ld.d
; CHECK: fsge.d
; CHECK: st.d
; CHECK: .size llvm_mips_fsge_d_test
;
@llvm_mips_fsgt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fsgt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fsgt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_fsgt_w_test() nounwind {
entry:
%0 = load <4 x float>* @llvm_mips_fsgt_w_ARG1
%1 = load <4 x float>* @llvm_mips_fsgt_w_ARG2
%2 = tail call <4 x i32> @llvm.mips.fsgt.w(<4 x float> %0, <4 x float> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_fsgt_w_RES
ret void
}
declare <4 x i32> @llvm.mips.fsgt.w(<4 x float>, <4 x float>) nounwind
; CHECK: llvm_mips_fsgt_w_test:
; CHECK: ld.w
; CHECK: ld.w
; CHECK: fsgt.w
; CHECK: st.w
; CHECK: .size llvm_mips_fsgt_w_test
;
@llvm_mips_fsgt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@llvm_mips_fsgt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
@llvm_mips_fsgt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_fsgt_d_test() nounwind {
entry:
%0 = load <2 x double>* @llvm_mips_fsgt_d_ARG1
%1 = load <2 x double>* @llvm_mips_fsgt_d_ARG2
%2 = tail call <2 x i64> @llvm.mips.fsgt.d(<2 x double> %0, <2 x double> %1)
store <2 x i64> %2, <2 x i64>* @llvm_mips_fsgt_d_RES
ret void
}
declare <2 x i64> @llvm.mips.fsgt.d(<2 x double>, <2 x double>) nounwind
; CHECK: llvm_mips_fsgt_d_test:
; CHECK: ld.d
; CHECK: ld.d
; CHECK: fsgt.d
; CHECK: st.d
; CHECK: .size llvm_mips_fsgt_d_test
;
@llvm_mips_fsle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fsle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fsle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16