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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1094,6 +1094,21 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
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unsigned P = fieldFromInstruction32(Insn, 24, 1);
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unsigned P = fieldFromInstruction32(Insn, 24, 1);
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bool writeback = (W == 1) | (P == 0);
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bool writeback = (W == 1) | (P == 0);
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// For {LD,ST}RD, Rt must be even, else undefined.
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switch (Inst.getOpcode()) {
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case ARM::STRD:
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case ARM::STRD_PRE:
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case ARM::STRD_POST:
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case ARM::LDRD:
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case ARM::LDRD_PRE:
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case ARM::LDRD_POST:
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if (Rt & 0x1) return false;
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break;
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default:
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break;
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}
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if (writeback) { // Writeback
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if (writeback) { // Writeback
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if (P)
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if (P)
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U |= ARMII::IndexModePre << 9;
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U |= ARMII::IndexModePre << 9;
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@ -104,21 +104,21 @@
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# LDRD (immediate)
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# LDRD (immediate)
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# CHECK: ldrd r3, r4, [r5
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# CHECK: ldrd r0, r1, [r5]
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# CHECK: ldrd r7, r8, [r2, #15
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# CHECK: ldrd r8, r9, [r2, #15]
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# CHECK: ldrd r1, r2, [r9, #32]!
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# CHECK: ldrd r2, r3, [r9, #32]!
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# CHECK: ldrd r6, r7, [r1], #8
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# CHECK: ldrd r6, r7, [r1], #8
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# CHECK: ldrd r1, r2, [r8], #0
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# CHECK: ldrd r2, r3, [r8], #0
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# CHECK: ldrd r1, r2, [r8], #0
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# CHECK: ldrd r2, r3, [r8], #0
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# CHECK: ldrd r1, r2, [r8], #-0
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# CHECK: ldrd r2, r3, [r8], #-0
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0xd0 0x30 0xc5 0xe1
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0xd0 0x00 0xc5 0xe1
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0xdf 0x70 0xc2 0xe1
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0xdf 0x80 0xc2 0xe1
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0xd0 0x12 0xe9 0xe1
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0xd0 0x22 0xe9 0xe1
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0xd8 0x60 0xc1 0xe0
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0xd8 0x60 0xc1 0xe0
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0xd0 0x10 0xc8 0xe0
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0xd0 0x20 0xc8 0xe0
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0xd0 0x10 0xc8 0xe0
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0xd0 0x20 0xc8 0xe0
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0xd0 0x10 0x48 0xe0
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0xd0 0x20 0x48 0xe0
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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@ -128,15 +128,15 @@
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# LDRD (register)
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# LDRD (register)
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# CHECK: ldrd r3, r4, [r1, r3
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# CHECK: ldrd r4, r5, [r1, r3]
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# CHECK: ldrd r4, r5, [r7, r2]!
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# CHECK: ldrd r4, r5, [r7, r2]!
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# CHECK: ldrd r1, r2, [r8], r12
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# CHECK: ldrd r0, r1, [r8], r12
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# CHECK: ldrd r1, r2, [r8], -r12
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# CHECK: ldrd r0, r1, [r8], -r12
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0xd3 0x30 0x81 0xe1
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0xd3 0x40 0x81 0xe1
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0xd2 0x40 0xa7 0xe1
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0xd2 0x40 0xa7 0xe1
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0xdc 0x10 0x88 0xe0
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0xdc 0x00 0x88 0xe0
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0xdc 0x10 0x08 0xe0
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0xdc 0x00 0x08 0xe0
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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@ -388,21 +388,21 @@
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# STRD (immediate)
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# STRD (immediate)
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# CHECK: strd r1, r2, [r4
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# CHECK: strd r0, r1, [r4]
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# CHECK: strd r2, r3, [r6, #1
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# CHECK: strd r2, r3, [r6, #1]
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# CHECK: strd r3, r4, [r7, #22]!
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# CHECK: strd r2, r3, [r7, #22]!
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# CHECK: strd r4, r5, [r8], #7
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# CHECK: strd r4, r5, [r8], #7
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# CHECK: strd r5, r6, [sp], #0
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# CHECK: strd r4, r5, [sp], #0
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# CHECK: strd r6, r7, [lr], #0
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# CHECK: strd r6, r7, [lr], #0
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# CHECK: strd r7, r8, [r9], #-0
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# CHECK: strd r6, r7, [r9], #-0
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0xf0 0x10 0xc4 0xe1
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0xf0 0x00 0xc4 0xe1
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0xf1 0x20 0xc6 0xe1
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0xf1 0x20 0xc6 0xe1
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0xf6 0x31 0xe7 0xe1
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0xf6 0x21 0xe7 0xe1
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0xf7 0x40 0xc8 0xe0
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0xf7 0x40 0xc8 0xe0
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0xf0 0x50 0xcd 0xe0
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0xf0 0x40 0xcd 0xe0
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0xf0 0x60 0xce 0xe0
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0xf0 0x60 0xce 0xe0
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0xf0 0x70 0x49 0xe0
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0xf0 0x60 0x49 0xe0
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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@ -412,16 +412,15 @@
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# STRD (register)
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# STRD (register)
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# CHECK: strd r8, r9, [r4, r1
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# CHECK: strd r8, r9, [r4, r1]
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# CHECK: strd r7, r8, [r3, r9]!
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# CHECK: strd r6, r7, [r3, r9]!
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# CHECK: strd r6, r7, [r5], r8
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# CHECK: strd r6, r7, [r5], r8
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# CHECK: strd r5, r6, [r12], -r10
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# CHECK: strd r4, r5, [r12], -r10
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0xf1 0x80 0x84 0xe1
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0xf1 0x80 0x84 0xe1
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0xf9 0x70 0xa3 0xe1
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0xf9 0x60 0xa3 0xe1
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0xf8 0x60 0x85 0xe0
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0xf8 0x60 0x85 0xe0
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0xfa 0x50 0x0c 0xe0
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0xfa 0x40 0x0c 0xe0
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# STRH (immediate)
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# STRH (immediate)
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