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[mips] Delete all floating point instruction classes that are no longer used.

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No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-13 02:05:02 +00:00
parent 25953bfb07
commit c567b1cd0d
3 changed files with 2 additions and 279 deletions
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33
lib/Target/Mips/MipsCondMov.td
View File

@ -25,37 +25,6 @@ class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
}
// cond:int, data:float
class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
bits<6> func, string instr_asm> :
FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
!strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
bits<5> rt;
let ft = rt;
let Constraints = "$F = $fd";
}
// cond:float, data:int
class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
string instr_asm> :
FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
!strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
[(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
let cc = 0;
let Uses = [FCR31];
let Constraints = "$F = $rd";
}
// cond:float, data:float
class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
string instr_asm> :
FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
!strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
[(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
let cc = 0;
let Uses = [FCR31];
let Constraints = "$F = $fd";
}
class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
InstrItinClass Itin> :
InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
@ -63,6 +32,7 @@ class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
let Constraints = "$F = $fd";
}
// cond:float, data:int
class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
@ -72,6 +42,7 @@ class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
let Constraints = "$F = $rd";
}
// cond:float, data:float
class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),

118
lib/Target/Mips/MipsInstrFPU.td
View File

@ -86,102 +86,6 @@ def fpimm0neg : PatLeaf<(fpimm), [{
// Only S32 and D32 are supported right now.
//===----------------------------------------------------------------------===//
// FP unary instructions without patterns.
class FFR1<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
RegisterClass SrcRC> :
FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
!strconcat(opstr, "\t$fd, $fs"), []> {
let ft = 0;
}
// FP unary instructions with patterns.
class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
RegisterClass SrcRC, SDNode OpNode> :
FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
!strconcat(opstr, "\t$fd, $fs"),
[(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
let ft = 0;
}
class FFR2P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass RC,
SDNode OpNode> :
FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
!strconcat(opstr, "\t$fd, $fs, $ft"),
[(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
// FP load.
let DecoderMethod = "DecodeFMem" in {
class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
IILoad>;
// FP store.
class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
!strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
IIStore>;
}
// FP indexed load.
class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
RegisterClass PRC, SDPatternOperator FOp = null_frag>:
FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
!strconcat(opstr, "\t$fd, ${index}(${base})"),
[(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
let fs = 0;
}
// FP indexed store.
class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
RegisterClass PRC, SDPatternOperator FOp= null_frag>:
FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
!strconcat(opstr, "\t$fs, ${index}(${base})"),
[(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
let fd = 0;
}
// Instructions that convert an FP value to 32-bit fixed point.
multiclass FFR1_W_M<bits<6> funct, string opstr> {
def _D32 : FFR1<funct, 17, opstr, FGR32, AFGR64>,
Requires<[NotFP64bit, HasStdEnc]>;
def _D64 : FFR1<funct, 17, opstr, FGR32, FGR64>,
Requires<[IsFP64bit, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}
// FP-to-FP conversion instructions.
multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
def _D32 : FFR1P<funct, 17, opstr, AFGR64, AFGR64, OpNode>,
Requires<[NotFP64bit, HasStdEnc]>;
def _D64 : FFR1P<funct, 17, opstr, FGR64, FGR64, OpNode>,
Requires<[IsFP64bit, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}
multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode> {
def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>,
Requires<[NotFP64bit, HasStdEnc]>;
def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>,
Requires<[IsFP64bit, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}
// FP madd/msub/nmadd/nmsub instruction classes.
class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
SDNode OpNode, RegisterClass RC> :
FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
[(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
SDNode OpNode, RegisterClass RC> :
FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
[(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
@ -360,13 +264,6 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
// When defining instructions, we reference all 32-bit registers,
// regardless of register aliasing.
class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
bits<5> rt;
let ft = rt;
let fd = 0;
}
/// Move Control Registers From/To CPU Registers
def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>;
def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>;
@ -503,16 +400,6 @@ let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
/// Floating Point Branch of False/True (Likely)
let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
[(MipsFPBrcond op, bb:$dst)]> {
let Inst{20-18} = 0;
let Inst{17} = nd;
let Inst{16} = tf;
}
let DecoderMethod = "DecodeBC1" in {
def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
@ -539,11 +426,6 @@ def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
!strconcat("c.$cc.", typestr, "\t$fs, $ft"),
[(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
/// Floating Point Compare
def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,

130
lib/Target/Mips/MipsInstrFormats.td
View File

@ -205,31 +205,6 @@ class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
//===----------------------------------------------------------------------===//
class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
string asmstr, list<dag> pattern> :
InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
{
bits<5> fd;
bits<5> fs;
bits<5> ft;
bits<5> fmt;
bits<6> funct;
let Opcode = op;
let funct = _funct;
let fmt = _fmt;
let Inst{25-21} = fmt;
let Inst{20-16} = ft;
let Inst{15-11} = fs;
let Inst{10-6} = fd;
let Inst{5-0} = funct;
}
//===----------------------------------------------------------------------===//
// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
//===----------------------------------------------------------------------===//
@ -248,111 +223,6 @@ class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
let Inst{15-0} = imm16;
}
//===----------------------------------------------------------------------===//
// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
//===----------------------------------------------------------------------===//
class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
{
bits<5> fs;
bits<5> ft;
bits<4> cc;
bits<5> fmt;
let Opcode = 0x11;
let fmt = _fmt;
let Inst{25-21} = fmt;
let Inst{20-16} = ft;
let Inst{15-11} = fs;
let Inst{10-6} = 0;
let Inst{5-4} = 0b11;
let Inst{3-0} = cc;
}
class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
list<dag> pattern> :
InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
{
bits<5> rd;
bits<5> rs;
bits<3> cc;
bits<1> tf;
let Opcode = 0;
let tf = _tf;
let Inst{25-21} = rs;
let Inst{20-18} = cc;
let Inst{17} = 0;
let Inst{16} = tf;
let Inst{15-11} = rd;
let Inst{10-6} = 0;
let Inst{5-0} = 1;
}
class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
list<dag> pattern> :
InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
{
bits<5> fd;
bits<5> fs;
bits<3> cc;
bits<5> fmt;
bits<1> tf;
let Opcode = 17;
let fmt = _fmt;
let tf = _tf;
let Inst{25-21} = fmt;
let Inst{20-18} = cc;
let Inst{17} = 0;
let Inst{16} = tf;
let Inst{15-11} = fs;
let Inst{10-6} = fd;
let Inst{5-0} = 17;
}
// Floating point madd/msub/nmadd/nmsub.
class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
list<dag> pattern>
: InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> {
bits<5> fd;
bits<5> fr;
bits<5> fs;
bits<5> ft;
let Opcode = 0x13;
let Inst{25-21} = fr;
let Inst{20-16} = ft;
let Inst{15-11} = fs;
let Inst{10-6} = fd;
let Inst{5-3} = funct;
let Inst{2-0} = fmt;
}
// FP indexed load/store instructions.
class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
list<dag> pattern> :
InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
{
bits<5> base;
bits<5> index;
bits<5> fs;
bits<5> fd;
let Opcode = 0x13;
let Inst{25-21} = base;
let Inst{20-16} = index;
let Inst{15-11} = fs;
let Inst{10-6} = fd;
let Inst{5-0} = funct;
}
class ADDS_FM<bits<6> funct, bits<5> fmt> {
bits<5> fd;
bits<5> fs;