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AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.
This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208605 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
5049ca67c2
commit
c56a5421b8
@ -1322,6 +1322,7 @@ def movimm64_shift : Operand<i32> {
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let PrintMethod = "printShifter";
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let ParserMatchClass = MovImm64ShifterOperand;
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}
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
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string asm>
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@ -365,6 +365,7 @@ defm MOVN : MoveImmediate<0b00, "movn">;
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let PostEncoderMethod = "fixMOVZ" in
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defm MOVZ : MoveImmediate<0b10, "movz">;
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// First group of aliases covers an implicit "lsl #0".
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def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
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def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
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def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
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@ -372,6 +373,7 @@ def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
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def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
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def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
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// Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
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def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
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def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
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def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
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@ -396,6 +398,40 @@ def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
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def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
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def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
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// Final group of aliases covers true "mov $Rd, $imm" cases.
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multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
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int width, int shift> {
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def _asmoperand : AsmOperandClass {
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let Name = basename # width # "_lsl" # shift # "MovAlias";
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let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
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# shift # ">";
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let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
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}
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def _movimm : Operand<i32> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
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}
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def : InstAlias<"mov $Rd, $imm",
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(INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
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}
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defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
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defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
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defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
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defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
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defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
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defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
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defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
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defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
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defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
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defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
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defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
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defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
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let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
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isAsCheapAsAMove = 1 in {
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// FIXME: The following pseudo instructions are only needed because remat
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@ -724,6 +724,44 @@ public:
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return isMovWSymbol(Variants);
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}
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template<int RegWidth, int Shift>
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bool isMOVZMovAlias() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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uint64_t Value = CE->getValue();
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if (RegWidth == 32)
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Value &= 0xffffffffULL;
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// "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
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if (Value == 0 && Shift != 0)
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return false;
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return (Value & ~(0xffffULL << Shift)) == 0;
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}
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template<int RegWidth, int Shift>
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bool isMOVNMovAlias() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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uint64_t Value = CE->getValue();
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// MOVZ takes precedence over MOVN.
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for (int MOVZShift = 0; MOVZShift <= 48; MOVZShift += 16)
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if ((Value & ~(0xffffULL << MOVZShift)) == 0)
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return false;
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Value = ~Value;
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if (RegWidth == 32)
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Value &= 0xffffffffULL;
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return (Value & ~(0xffffULL << Shift)) == 0;
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}
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bool isFPImm() const { return Kind == k_FPImm; }
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bool isBarrier() const { return Kind == k_Barrier; }
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bool isSysReg() const { return Kind == k_SysReg; }
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@ -1473,6 +1511,24 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Imm));
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}
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template<int Shift>
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void addMOVZMovAliasOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
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uint64_t Value = CE->getValue();
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Inst.addOperand(MCOperand::CreateImm((Value >> Shift) & 0xffff));
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}
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template<int Shift>
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void addMOVNMovAliasOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
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uint64_t Value = CE->getValue();
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Inst.addOperand(MCOperand::CreateImm((~Value >> Shift) & 0xffff));
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}
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void addMemoryRegisterOffsetOperands(MCInst &Inst, unsigned N, bool DoShift) {
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assert(N == 3 && "Invalid number of operands!");
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@ -3723,63 +3779,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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StringRef Tok = Op->getToken();
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unsigned NumOperands = Operands.size();
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if (Tok == "mov" && NumOperands == 3) {
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// The MOV mnemomic is aliased to movn/movz, depending on the value of
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// the immediate being instantiated.
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// FIXME: Catching this here is a total hack, and we should use tblgen
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// support to implement this instead as soon as it is available.
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ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
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if (Op2->isImm()) {
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op2->getImm())) {
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uint64_t Val = CE->getValue();
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uint64_t NVal = ~Val;
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// If this is a 32-bit register and the value has none of the upper
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// set, clear the complemented upper 32-bits so the logic below works
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// for 32-bit registers too.
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ARM64Operand *Op1 = static_cast<ARM64Operand *>(Operands[1]);
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if (Op1->isReg() &&
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ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(
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Op1->getReg()) &&
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(Val & 0xFFFFFFFFULL) == Val)
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NVal &= 0x00000000FFFFFFFFULL;
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// MOVK Rd, imm << 0
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if ((Val & 0xFFFF) == Val)
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rewriteMOVI(Operands, "movz", Val, 0, getContext());
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// MOVK Rd, imm << 16
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else if ((Val & 0xFFFF0000ULL) == Val)
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rewriteMOVI(Operands, "movz", Val, 16, getContext());
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// MOVK Rd, imm << 32
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else if ((Val & 0xFFFF00000000ULL) == Val)
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rewriteMOVI(Operands, "movz", Val, 32, getContext());
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// MOVK Rd, imm << 48
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else if ((Val & 0xFFFF000000000000ULL) == Val)
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rewriteMOVI(Operands, "movz", Val, 48, getContext());
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// MOVN Rd, (~imm << 0)
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else if ((NVal & 0xFFFFULL) == NVal)
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rewriteMOVI(Operands, "movn", NVal, 0, getContext());
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// MOVN Rd, ~(imm << 16)
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else if ((NVal & 0xFFFF0000ULL) == NVal)
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rewriteMOVI(Operands, "movn", NVal, 16, getContext());
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// MOVN Rd, ~(imm << 32)
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else if ((NVal & 0xFFFF00000000ULL) == NVal)
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rewriteMOVI(Operands, "movn", NVal, 32, getContext());
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// MOVN Rd, ~(imm << 48)
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else if ((NVal & 0xFFFF000000000000ULL) == NVal)
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rewriteMOVI(Operands, "movn", NVal, 48, getContext());
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}
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}
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} else if (NumOperands == 4) {
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if (NumOperands == 4 && Tok == "lsl") {
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if (NumOperands == 4 && Tok == "lsl") {
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ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
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ARM64Operand *Op3 = static_cast<ARM64Operand *>(Operands[3]);
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if (Op2->isReg() && Op3->isImm()) {
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@ -3812,7 +3812,6 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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delete Op;
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}
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}
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// FIXME: Horrible hack to handle the optional LSL shift for vector
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// instructions.
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} else if (NumOperands == 4 && (Tok == "bic" || Tok == "orr")) {
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