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https://github.com/c64scene-ar/llvm-6502.git
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[x86] Make the x86 PACKSSWB, PACKSSDW, PACKUSWB, and PACKUSDW
instructions available as synthetic SDNodes PACKSS and PACKUS that will select to the correct instruction variants based on the return type. This allows us to use these rather important instructions when lowering vector shuffles. Also moves the relevant instruction definitions to be split out from the fully generic multiclasses to allow them to match these new SDNodes in the same way that the UNPCK instructions do. No functionality should actually be changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211332 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
160dcf5b61
commit
c577e71bf5
@ -12513,6 +12513,20 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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Op.getOperand(1), Op.getOperand(2));
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}
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case Intrinsic::x86_sse2_packssdw_128:
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case Intrinsic::x86_sse2_packsswb_128:
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case Intrinsic::x86_avx2_packssdw:
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case Intrinsic::x86_avx2_packsswb:
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return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_sse2_packuswb_128:
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case Intrinsic::x86_sse41_packusdw:
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case Intrinsic::x86_avx2_packuswb:
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case Intrinsic::x86_avx2_packusdw:
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return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_ssse3_pshuf_b_128:
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case Intrinsic::x86_avx2_pshuf_b:
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return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
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@ -15286,6 +15300,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::TESTM: return "X86ISD::TESTM";
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case X86ISD::TESTNM: return "X86ISD::TESTNM";
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case X86ISD::KORTEST: return "X86ISD::KORTEST";
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case X86ISD::PACKSS: return "X86ISD::PACKSS";
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case X86ISD::PACKUS: return "X86ISD::PACKUS";
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case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
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case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
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case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
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@ -315,6 +315,8 @@ namespace llvm {
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KORTEST,
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// Several flavors of instructions with vector shuffle behaviors.
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PACKSS,
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PACKUS,
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PALIGNR,
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PSHUFD,
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PSHUFHW,
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@ -224,6 +224,10 @@ def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
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def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
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def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
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def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
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def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
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def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
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def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
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def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
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@ -4336,20 +4336,6 @@ defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
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defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
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SSE_INTALU_ITINS_P, 0>;
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Pack Instructions
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//===---------------------------------------------------------------------===//
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defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
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int_x86_avx2_packsswb,
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SSE_INTALU_ITINS_SHUFF_P, 0>;
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defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
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int_x86_avx2_packssdw,
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SSE_INTALU_ITINS_SHUFF_P, 0>;
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defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
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int_x86_avx2_packuswb,
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SSE_INTALU_ITINS_SHUFF_P, 0>;
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Shuffle Instructions
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//===---------------------------------------------------------------------===//
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@ -4431,6 +4417,136 @@ let Predicates = [UseSSE2] in {
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(PSHUFDri VR128:$src1, imm:$imm)>;
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}
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//===---------------------------------------------------------------------===//
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// Packed Integer Pack Instructions (SSE & AVX)
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//===---------------------------------------------------------------------===//
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let ExeDomain = SSEPackedInt in {
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multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
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bit Is2Addr = 1> {
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def rr : PDI<opc, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
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Sched<[WriteShuffle]>;
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def rm : PDI<opc, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode VR128:$src1,
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(bc_frag (memopv2i64 addr:$src2)))))]>,
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Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
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def Yrr : PDI<opc, MRMSrcReg,
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(outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
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Sched<[WriteShuffle]>;
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def Yrm : PDI<opc, MRMSrcMem,
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(outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode VR256:$src1,
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(bc_frag (memopv4i64 addr:$src2)))))]>,
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Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
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bit Is2Addr = 1> {
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def rr : SS48I<opc, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
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Sched<[WriteShuffle]>;
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def rm : SS48I<opc, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode VR128:$src1,
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(bc_frag (memopv2i64 addr:$src2)))))]>,
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Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
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def Yrr : SS48I<opc, MRMSrcReg,
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(outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
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Sched<[WriteShuffle]>;
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def Yrm : SS48I<opc, MRMSrcMem,
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(outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode VR256:$src1,
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(bc_frag (memopv4i64 addr:$src2)))))]>,
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Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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let Predicates = [HasAVX] in {
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defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
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bc_v8i16, 0>, VEX_4V;
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defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
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bc_v4i32, 0>, VEX_4V;
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defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
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bc_v8i16, 0>, VEX_4V;
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defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
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bc_v4i32, 0>, VEX_4V;
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}
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let Predicates = [HasAVX2] in {
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defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
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bc_v16i16>, VEX_4V, VEX_L;
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defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
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bc_v8i32>, VEX_4V, VEX_L;
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defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
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bc_v16i16>, VEX_4V, VEX_L;
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defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
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bc_v8i32>, VEX_4V, VEX_L;
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}
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let Constraints = "$src1 = $dst" in {
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defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
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bc_v8i16>;
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defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
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bc_v4i32>;
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defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
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bc_v8i16>;
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let Predicates = [HasSSE41] in
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defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
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bc_v4i32>;
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}
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} // ExeDomain = SSEPackedInt
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Unpack Instructions
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//===---------------------------------------------------------------------===//
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@ -7053,8 +7169,6 @@ multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
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let Predicates = [HasAVX] in {
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let isCommutable = 0 in
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defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
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0, DEFAULT_ITINS_SHUFFLESCHED>, VEX_4V;
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defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
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loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
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VEX_4V;
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@ -7086,9 +7200,6 @@ let Predicates = [HasAVX] in {
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let Predicates = [HasAVX2] in {
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let isCommutable = 0 in
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defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
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int_x86_avx2_packusdw, WriteShuffle>,
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VEX_4V, VEX_L;
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defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
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loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
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VEX_4V, VEX_L;
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@ -7120,8 +7231,6 @@ let Predicates = [HasAVX2] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in
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defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw,
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1, DEFAULT_ITINS_SHUFFLESCHED>;
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defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
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memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
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defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
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