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ARM disassembler was erroneously accepting an invalid LSL instruction.

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For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-05 21:49:44 +00:00
parent 7670601313
commit c584e317e9
2 changed files with 13 additions and 0 deletions
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4
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1068,6 +1068,10 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
if (Rs) {
// If Inst{7} != 0, we should reject this insn as an invalid encoding.
if (slice(insn, 7, 7))
return false;
// Register-controlled shifts: [Rm, Rs, shift].
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRs(insn))));