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ARM extend instructions simplification.

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Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-27 16:47:19 +00:00
parent ffcc2a542c
commit c5a8c861c9
5 changed files with 87 additions and 89 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/ARMFastISel.cpp
View File

@@ -2003,15 +2003,15 @@ bool ARMFastISel::SelectIntCast(const Instruction *I) {
default: return false; default: return false;
case MVT::i16: case MVT::i16:
if (isZext) if (isZext)
Opc = isThumb ? ARM::t2UXTHr : ARM::UXTHr; Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
else else
Opc = isThumb ? ARM::t2SXTHr : ARM::SXTHr; Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
break; break;
case MVT::i8: case MVT::i8:
if (isZext) if (isZext)
Opc = isThumb ? ARM::t2UXTBr : ARM::UXTBr; Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
else else
Opc = isThumb ? ARM::t2SXTBr : ARM::SXTBr; Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
break; break;
case MVT::i1: case MVT::i1:
if (isZext) { if (isZext) {
@@ -2033,6 +2033,8 @@ bool ARMFastISel::SelectIntCast(const Instruction *I) {
.addReg(SrcReg); .addReg(SrcReg);
if (isBoolZext) if (isBoolZext)
MIB.addImm(1); MIB.addImm(1);
else
MIB.addImm(0);
AddOptionalDefs(MIB); AddOptionalDefs(MIB);
UpdateValueMap(I, DestReg); UpdateValueMap(I, DestReg);
return true; return true;

8
lib/Target/ARM/ARMISelLowering.cpp
View File

@@ -5125,12 +5125,12 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
case 1: case 1:
ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
extendOpc = isThumb2 ? ARM::t2SXTBr : ARM::SXTBr; extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
break; break;
case 2: case 2:
ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
extendOpc = isThumb2 ? ARM::t2SXTHr : ARM::SXTHr; extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
break; break;
case 4: case 4:
ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
@@ -5175,7 +5175,9 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
// Sign extend the value, if necessary. // Sign extend the value, if necessary.
if (signExtend && extendOpc) { if (signExtend && extendOpc) {
oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest)); AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
.addReg(dest)
.addImm(0));
} }
// Build compare and cmov instructions. // Build compare and cmov instructions.

83
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -986,48 +986,27 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
/// AI_ext_rrot - A unary operation with two forms: one whose operand is a /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
/// FIXME: Remove the 'r' variant. Its rot_imm is zero. /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> { class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm), : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm", IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[(set GPR:$Rd, (opnode GPR:$Rm))]>, [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
bits<4> Rd; bits<4> Rd;
bits<4> Rm; bits<4> Rm;
let Inst{19-16} = 0b1111; bits<2> rot;
let Inst{15-12} = Rd; let Inst{19-16} = 0b1111;
let Inst{11-10} = 0b00; let Inst{15-12} = Rd;
let Inst{3-0} = Rm; let Inst{11-10} = rot;
} let Inst{3-0} = Rm;
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
bits<4> Rd;
bits<4> Rm;
bits<2> rot;
let Inst{19-16} = 0b1111;
let Inst{15-12} = Rd;
let Inst{11-10} = rot;
let Inst{3-0} = Rm;
}
} }
multiclass AI_ext_rrot_np<bits<8> opcod, string opc> { class AI_ext_rrot_np<bits<8> opcod, string opc>
def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm), : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm", IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
[/* For disassembly only; pattern left blank */]>, Requires<[IsARM, HasV6]> {
Requires<[IsARM, HasV6]> { bits<2> rot;
let Inst{19-16} = 0b1111; let Inst{19-16} = 0b1111;
let Inst{11-10} = 0b00; let Inst{11-10} = rot;
}
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
bits<2> rot;
let Inst{19-16} = 0b1111;
let Inst{11-10} = rot;
}
} }
/// AI_exta_rrot - A binary operation with two forms: one whose operand is a /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
@@ -2393,9 +2372,9 @@ def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
// Sign extenders // Sign extenders
defm SXTB : AI_ext_rrot<0b01101010, def SXTB : AI_ext_rrot<0b01101010,
"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
defm SXTH : AI_ext_rrot<0b01101011, def SXTH : AI_ext_rrot<0b01101011,
"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
defm SXTAB : AI_exta_rrot<0b01101010, defm SXTAB : AI_exta_rrot<0b01101010,
@@ -2403,20 +2382,18 @@ defm SXTAB : AI_exta_rrot<0b01101010,
defm SXTAH : AI_exta_rrot<0b01101011, defm SXTAH : AI_exta_rrot<0b01101011,
"sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
// For disassembly only def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
// For disassembly only
defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
// Zero extenders // Zero extenders
let AddedComplexity = 16 in { let AddedComplexity = 16 in {
defm UXTB : AI_ext_rrot<0b01101110, def UXTB : AI_ext_rrot<0b01101110,
"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
defm UXTH : AI_ext_rrot<0b01101111, def UXTH : AI_ext_rrot<0b01101111,
"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
defm UXTB16 : AI_ext_rrot<0b01101100, def UXTB16 : AI_ext_rrot<0b01101100,
"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
// FIXME: This pattern incorrectly assumes the shl operator is a rotate. // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
@@ -2426,7 +2403,7 @@ defm UXTB16 : AI_ext_rrot<0b01101100,
//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
// (UXTB16r_rot GPR:$Src, 3)>; // (UXTB16r_rot GPR:$Src, 3)>;
def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
(UXTB16r_rot GPR:$Src, 1)>; (UXTB16 GPR:$Src, 1)>;
defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
@@ -4287,6 +4264,14 @@ def : ARMV5TEPat<(add GPR:$acc,
def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
// SXT/UXT with no rotate
def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
let AddedComplexity = 10 in
def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Thumb Support // Thumb Support

57
lib/Target/ARM/ARMInstrThumb2.td
View File

@@ -977,31 +977,19 @@ multiclass T2I_st<bits<2> opcod, string opc,
/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> { class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr, : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
opc, ".w\t$Rd, $Rm", opc, ".w\t$Rd, $Rm$rot",
[(set rGPR:$Rd, (opnode rGPR:$Rm))]> { [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
let Inst{19-16} = 0b1111; // Rn let Inst{19-16} = 0b1111; // Rn
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
let Inst{7} = 1; let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate
}
def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
opc, ".w\t$Rd, $Rm$rot",
[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{19-16} = 0b1111; // Rn
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
bits<2> rot; bits<2> rot;
let Inst{5-4} = rot{1-0}; // rotate let Inst{5-4} = rot{1-0}; // rotate
}
} }
// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
@@ -1669,9 +1657,9 @@ def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
// Sign extenders // Sign extenders
defm t2SXTB : T2I_ext_rrot<0b100, "sxtb", def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
UnOpFrag<(sext_inreg node:$Src, i8)>>; UnOpFrag<(sext_inreg node:$Src, i8)>>;
defm t2SXTH : T2I_ext_rrot<0b000, "sxth", def t2SXTH : T2I_ext_rrot<0b000, "sxth",
UnOpFrag<(sext_inreg node:$Src, i16)>>; UnOpFrag<(sext_inreg node:$Src, i16)>>;
defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
@@ -1686,9 +1674,9 @@ defm t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
// Zero extenders // Zero extenders
let AddedComplexity = 16 in { let AddedComplexity = 16 in {
defm t2UXTB : T2I_ext_rrot<0b101, "uxtb", def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
UnOpFrag<(and node:$Src, 0x000000FF)>>; UnOpFrag<(and node:$Src, 0x000000FF)>>;
defm t2UXTH : T2I_ext_rrot<0b001, "uxth", def t2UXTH : T2I_ext_rrot<0b001, "uxth",
UnOpFrag<(and node:$Src, 0x0000FFFF)>>; UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
UnOpFrag<(and node:$Src, 0x00FF00FF)>>; UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
@@ -3462,3 +3450,16 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
let Inst{19-16} = CRn; let Inst{19-16} = CRn;
let Inst{23-20} = opc1; let Inst{23-20} = opc1;
} }
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//
// SXT/UXT with no rotate
def : T2Pat<(and rGPR:$Src, 0x000000FF), (t2UXTB rGPR:$Src, 0)>;
def : T2Pat<(and rGPR:$Src, 0x0000FFFF), (t2UXTH rGPR:$Src, 0)>;
def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>;
def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>;

18
lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@@ -97,11 +97,11 @@ namespace {
{ ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 }, { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 },
{ ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 }, { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 },
{ ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 }, { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 },
{ ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,0 }, { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1 },
{ ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,0 }, { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1 },
{ ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 }, { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 },
{ ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,0 }, { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1 },
{ ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,0 }, { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1 },
// FIXME: Clean this up after splitting each Thumb load / store opcode // FIXME: Clean this up after splitting each Thumb load / store opcode
// into multiple ones. // into multiple ones.
@@ -546,6 +546,10 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
} }
case ARM::t2RSBri: case ARM::t2RSBri:
case ARM::t2RSBSri: case ARM::t2RSBSri:
case ARM::t2SXTB:
case ARM::t2SXTH:
case ARM::t2UXTB:
case ARM::t2UXTH:
if (MI->getOperand(2).getImm() == 0) if (MI->getOperand(2).getImm() == 0)
return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
break; break;
@@ -742,7 +746,11 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
continue; continue;
if ((MCID.getOpcode() == ARM::t2RSBSri || if ((MCID.getOpcode() == ARM::t2RSBSri ||
MCID.getOpcode() == ARM::t2RSBri) && i == 2) MCID.getOpcode() == ARM::t2RSBri ||
MCID.getOpcode() == ARM::t2SXTB ||
MCID.getOpcode() == ARM::t2SXTH ||
MCID.getOpcode() == ARM::t2UXTB ||
MCID.getOpcode() == ARM::t2UXTH) && i == 2)
// Skip the zero immediate operand, it's now implicit. // Skip the zero immediate operand, it's now implicit.
continue; continue;
bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());