From c5ca284e8527696db9e9daaa5ee04baeec26e36b Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Mon, 4 Aug 2014 23:41:27 +0000 Subject: [PATCH] Merging r214716: ------------------------------------------------------------------------ r214716 | uweigand | 2014-08-04 08:27:12 -0500 (Mon, 04 Aug 2014) | 9 lines [PowerPC] MULHU/MULHS are not legal for vector types I ran into some test failures where common code changed vector division by constant into a multiply-high operation (MULHU). But these are not implemented by the back-end, so we failed to recognize the insn. Fixed by marking MULHU/MULHS as Expand for vector types. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214818 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 2 ++ test/CodeGen/PowerPC/vec_urem_const.ll | 10 ++++++++++ 2 files changed, 12 insertions(+) create mode 100644 test/CodeGen/PowerPC/vec_urem_const.ll diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 634d902e566..5aec9dc2a73 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -453,6 +453,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); setOperationAction(ISD::BUILD_VECTOR, VT, Expand); + setOperationAction(ISD::MULHU, VT, Expand); + setOperationAction(ISD::MULHS, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand); setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::UDIVREM, VT, Expand); diff --git a/test/CodeGen/PowerPC/vec_urem_const.ll b/test/CodeGen/PowerPC/vec_urem_const.ll new file mode 100644 index 00000000000..a562c3bb359 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_urem_const.ll @@ -0,0 +1,10 @@ +; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s + +; Common code used to replace the urem by a mulhu, and compilation would +; then crash since mulhu isn't supported on vector types. + +define <4 x i32> @test(<4 x i32> %x) { +entry: + %0 = urem <4 x i32> %x, + ret <4 x i32> %0 +}