mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Merging r214716:
------------------------------------------------------------------------ r214716 | uweigand | 2014-08-04 08:27:12 -0500 (Mon, 04 Aug 2014) | 9 lines [PowerPC] MULHU/MULHS are not legal for vector types I ran into some test failures where common code changed vector division by constant into a multiply-high operation (MULHU). But these are not implemented by the back-end, so we failed to recognize the insn. Fixed by marking MULHU/MULHS as Expand for vector types. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214818 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
39f807fc9f
commit
c5ca284e85
@ -453,6 +453,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
|
||||
setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
|
||||
setOperationAction(ISD::MULHU, VT, Expand);
|
||||
setOperationAction(ISD::MULHS, VT, Expand);
|
||||
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
|
||||
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
|
||||
setOperationAction(ISD::UDIVREM, VT, Expand);
|
||||
|
10
test/CodeGen/PowerPC/vec_urem_const.ll
Normal file
10
test/CodeGen/PowerPC/vec_urem_const.ll
Normal file
@ -0,0 +1,10 @@
|
||||
; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s
|
||||
|
||||
; Common code used to replace the urem by a mulhu, and compilation would
|
||||
; then crash since mulhu isn't supported on vector types.
|
||||
|
||||
define <4 x i32> @test(<4 x i32> %x) {
|
||||
entry:
|
||||
%0 = urem <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
|
||||
ret <4 x i32> %0
|
||||
}
|
Loading…
Reference in New Issue
Block a user