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Convert more static tables of registers used by calling convention to uint16_t to reduce space.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-03-11 07:57:25 +00:00
parent b78ca42384
commit c5eaae4e9b
12 changed files with 44 additions and 44 deletions
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12
include/llvm/CodeGen/CallingConvLower.h
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@ -229,7 +229,7 @@ public:
/// getFirstUnallocated - Return the first unallocated register in the set, or
/// NumRegs if they are all allocated.
unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const {
for (unsigned i = 0; i != NumRegs; ++i)
if (!isAllocated(Regs[i]))
return i;
@ -256,7 +256,7 @@ public:
/// AllocateReg - Attempt to allocate one of the specified registers. If none
/// are available, return zero. Otherwise, return the first one available,
/// marking it and any aliases as allocated.
unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
if (FirstUnalloc == NumRegs)
return 0; // Didn't find the reg.
@ -268,7 +268,7 @@ public:
}
/// Version of AllocateReg with list of registers to be shadowed.
unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs,
unsigned NumRegs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
if (FirstUnalloc == NumRegs)
@ -306,12 +306,12 @@ public:
// First GPR that carries part of a byval aggregate that's split
// between registers and memory.
unsigned getFirstByValReg() { return FirstByValRegValid ? FirstByValReg : 0; }
unsigned getFirstByValReg() const { return FirstByValRegValid ? FirstByValReg : 0; }
void setFirstByValReg(unsigned r) { FirstByValReg = r; FirstByValRegValid = true; }
void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false; }
bool isFirstByValRegValid() { return FirstByValRegValid; }
bool isFirstByValRegValid() const { return FirstByValRegValid; }
ParmContext getCallOrPrologue() { return CallOrPrologue; }
ParmContext getCallOrPrologue() const { return CallOrPrologue; }
private:
/// MarkAllocated - Mark a register and all of its aliases as allocated.

12
lib/Target/ARM/ARMCallingConv.h
View File

@ -29,7 +29,7 @@ namespace llvm {
static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
CCState &State, bool CanFail) {
static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
// Try to get the first register.
if (unsigned Reg = State.AllocateReg(RegList, 4))
@ -72,9 +72,9 @@ static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
CCState &State, bool CanFail) {
static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 };
static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
static const uint16_t ShadowRegList[] = { ARM::R0, ARM::R1 };
unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
if (Reg == 0) {
@ -118,8 +118,8 @@ static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo, CCState &State) {
static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
if (Reg == 0)

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -87,7 +87,7 @@ namespace {
}
// The APCS parameter registers.
static const unsigned GPRArgRegs[] = {
static const uint16_t GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
};

6
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -159,7 +159,7 @@ static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
static const unsigned RegList[] = {
static const uint16_t RegList[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5
};
@ -182,10 +182,10 @@ static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
return false;
}
static const unsigned RegList1[] = {
static const uint16_t RegList1[] = {
Hexagon::D1, Hexagon::D2
};
static const unsigned RegList2[] = {
static const uint16_t RegList2[] = {
Hexagon::R1, Hexagon::R3
};
if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {

2
lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -657,7 +657,7 @@ static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
static const unsigned ArgRegs[] = {
static const uint16_t ArgRegs[] = {
MBlaze::R5, MBlaze::R6, MBlaze::R7,
MBlaze::R8, MBlaze::R9, MBlaze::R10
};

20
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -1875,13 +1875,13 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
static const unsigned IntRegsSize=4, FloatRegsSize=2;
static const unsigned IntRegs[] = {
static const uint16_t IntRegs[] = {
Mips::A0, Mips::A1, Mips::A2, Mips::A3
};
static const unsigned F32Regs[] = {
static const uint16_t F32Regs[] = {
Mips::F12, Mips::F14
};
static const unsigned F64Regs[] = {
static const uint16_t F64Regs[] = {
Mips::D6, Mips::D7
};
@ -1960,10 +1960,10 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
return false; // CC must always match
}
static const unsigned Mips64IntRegs[8] =
static const uint16_t Mips64IntRegs[8] =
{Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
static const unsigned Mips64DPRegs[8] =
static const uint16_t Mips64DPRegs[8] =
{Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
@ -2030,7 +2030,7 @@ AnalyzeMips64CallOperands(CCState &CCInfo,
static const unsigned O32IntRegsSize = 4;
static const unsigned O32IntRegs[] = {
static const uint16_t O32IntRegs[] = {
Mips::A0, Mips::A1, Mips::A2, Mips::A3
};
@ -2149,9 +2149,9 @@ PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
if (!IsRegLoc)
LocMemOffset = VA.getLocMemOffset();
else {
const unsigned *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
VA.getLocReg());
const unsigned *RegEnd = Mips64IntRegs + 8;
const uint16_t *RegEnd = Mips64IntRegs + 8;
// Copy double words to registers.
for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
@ -2574,7 +2574,7 @@ CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
MachineFrameInfo *MFI, bool IsRegLoc,
SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
EVT PtrTy) {
const unsigned *Reg = Mips64IntRegs + 8;
const uint16_t *Reg = Mips64IntRegs + 8;
int FOOffset; // Frame object offset from virtual frame pointer.
if (IsRegLoc) {
@ -2743,7 +2743,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
if (isVarArg) {
unsigned NumOfRegs = IsO32 ? 4 : 8;
const unsigned *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
const TargetRegisterClass *RC

8
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1547,7 +1547,7 @@ static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
static const unsigned ArgRegs[] = {
static const uint16_t ArgRegs[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
@ -1574,7 +1574,7 @@ static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
static const unsigned ArgRegs[] = {
static const uint16_t ArgRegs[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8
};
@ -1780,13 +1780,13 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
// If the function takes variable number of arguments, make a frame index for
// the start of the first vararg value... for expansion of llvm.va_start.
if (isVarArg) {
static const unsigned GPArgRegs[] = {
static const uint16_t GPArgRegs[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
static const unsigned FPArgRegs[] = {
static const uint16_t FPArgRegs[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8
};

6
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -50,7 +50,7 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
MVT &LocVT, CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, CCState &State)
{
static const unsigned RegList[] = {
static const uint16_t RegList[] = {
SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
};
//Try to get first reg
@ -301,11 +301,11 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
// Store remaining ArgRegs to the stack if this is a varargs function.
if (isVarArg) {
static const unsigned ArgRegs[] = {
static const uint16_t ArgRegs[] = {
SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
};
unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
unsigned ArgOffset = CCInfo.getNextStackOffset();
if (NumAllocated == 6)
ArgOffset += StackOffset;

2
lib/Target/X86/X86FastISel.cpp
View File

@ -1779,7 +1779,7 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64()) {
// Count the number of XMM registers allocated.
static const unsigned XMMArgRegs[] = {
static const uint16_t XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};

10
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1927,17 +1927,17 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
// FIXME: We should really autogenerate these arrays
static const unsigned GPR64ArgRegsWin64[] = {
static const uint16_t GPR64ArgRegsWin64[] = {
X86::RCX, X86::RDX, X86::R8, X86::R9
};
static const unsigned GPR64ArgRegs64Bit[] = {
static const uint16_t GPR64ArgRegs64Bit[] = {
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
};
static const unsigned XMMArgRegs64Bit[] = {
static const uint16_t XMMArgRegs64Bit[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
const unsigned *GPR64ArgRegs;
const uint16_t *GPR64ArgRegs;
unsigned NumXMMRegs = 0;
if (IsWin64) {
@ -2326,7 +2326,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// registers used and is in the range 0 - 8 inclusive.
// Count the number of XMM registers allocated.
static const unsigned XMMArgRegs[] = {
static const uint16_t XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};

2
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -1152,7 +1152,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
if (isVarArg) {
/* Argument registers */
static const unsigned ArgRegs[] = {
static const uint16_t ArgRegs[] = {
XCore::R0, XCore::R1, XCore::R2, XCore::R3
};
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();

6
utils/TableGen/CallingConvEmitter.cpp
View File

@ -96,7 +96,7 @@ void CallingConvEmitter::EmitAction(Record *Action,
O << IndentStr << "if (unsigned Reg = State.AllocateReg(";
O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n";
} else {
O << IndentStr << "static const unsigned RegList" << ++Counter
O << IndentStr << "static const uint16_t RegList" << ++Counter
<< "[] = {\n";
O << IndentStr << " ";
for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
@ -127,7 +127,7 @@ void CallingConvEmitter::EmitAction(Record *Action,
unsigned RegListNumber = ++Counter;
unsigned ShadowRegListNumber = ++Counter;
O << IndentStr << "static const unsigned RegList" << RegListNumber
O << IndentStr << "static const uint16_t RegList" << RegListNumber
<< "[] = {\n";
O << IndentStr << " ";
for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
@ -136,7 +136,7 @@ void CallingConvEmitter::EmitAction(Record *Action,
}
O << "\n" << IndentStr << "};\n";
O << IndentStr << "static const unsigned RegList"
O << IndentStr << "static const uint16_t RegList"
<< ShadowRegListNumber << "[] = {\n";
O << IndentStr << " ";
for (unsigned i = 0, e = ShadowRegList->getSize(); i != e; ++i) {