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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
80 column cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -53,9 +53,9 @@ def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
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"Disable VFP MAC instructions">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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@ -2326,8 +2326,8 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
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let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
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Defs = [CPSR] in {
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def BCCi64 : PseudoInst<(outs),
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(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
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IIC_Br,
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(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
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IIC_Br,
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"${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, imm:$cc",
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[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
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@ -1731,7 +1731,8 @@ def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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// Extra precision multiplies with low / high results
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let neverHasSideEffects = 1 in {
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let isCommutable = 1 in {
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def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
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def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
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(ins rGPR:$a, rGPR:$b), IIC_iMUL64,
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"smull", "\t$ldst, $hdst, $a, $b", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0111;
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@ -1739,7 +1740,8 @@ def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMU
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let Inst{7-4} = 0b0000;
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}
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def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
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def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
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(ins rGPR:$a, rGPR:$b), IIC_iMUL64,
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"umull", "\t$ldst, $hdst, $a, $b", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0111;
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@ -1749,7 +1751,8 @@ def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMU
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} // isCommutable
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// Multiply + accumulate
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def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
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def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
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(ins rGPR:$a, rGPR:$b), IIC_iMAC64,
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"smlal", "\t$ldst, $hdst, $a, $b", []>{
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0111;
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@ -1757,7 +1760,8 @@ def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMA
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let Inst{7-4} = 0b0000;
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}
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def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
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def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
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(ins rGPR:$a, rGPR:$b), IIC_iMAC64,
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"umlal", "\t$ldst, $hdst, $a, $b", []>{
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0111;
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@ -1765,7 +1769,8 @@ def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMA
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let Inst{7-4} = 0b0000;
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}
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def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
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def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
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(ins rGPR:$a, rGPR:$b), IIC_iMAC64,
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"umaal", "\t$ldst, $hdst, $a, $b", []>{
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0111;
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@ -1806,7 +1811,7 @@ def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
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}
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def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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"smmlar", "\t$dst, $a, $b, $c", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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@ -1815,7 +1820,7 @@ def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32
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let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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}
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def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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"smmls", "\t$dst, $a, $b, $c",
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[(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
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let Inst{31-27} = 0b11111;
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@ -1825,7 +1830,7 @@ def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32
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let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
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}
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def t2SMMLSR : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
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"smmlsr", "\t$dst, $a, $b, $c", []> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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@ -1926,7 +1931,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
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!strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
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[(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
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(sra rGPR:$b, (i32 16)))))]> {
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(sra rGPR:$b, (i32 16)))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -1938,7 +1943,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
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!strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
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[(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
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(sext_inreg rGPR:$b, i16))))]> {
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(sext_inreg rGPR:$b, i16))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -1950,7 +1955,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
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!strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
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[(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
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(sra rGPR:$b, (i32 16)))))]> {
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(sra rGPR:$b, (i32 16)))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -1962,7 +1967,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
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!strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
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[(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
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(sext_inreg rGPR:$b, i16)), (i32 16))))]> {
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(sext_inreg rGPR:$b, i16)), (i32 16))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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@ -1974,7 +1979,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
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!strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
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[(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
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(sra rGPR:$b, (i32 16))), (i32 16))))]> {
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(sra rGPR:$b, (i32 16))), (i32 16))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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@ -1989,35 +1994,35 @@ defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
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def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
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(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
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// These are for disassembly only.
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def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
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def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
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def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
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def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
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def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
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IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
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@ -2068,7 +2073,7 @@ def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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[(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
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def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
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"rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
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def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"rev16", ".w\t$dst, $src",
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@ -2076,7 +2081,7 @@ def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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(or (and (srl rGPR:$src, (i32 8)), 0xFF),
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(or (and (shl rGPR:$src, (i32 8)), 0xFF00),
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(or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
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(and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
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(and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
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def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"revsh", ".w\t$dst, $src",
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