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Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
15c260adff
commit
c64a1a921c
@ -119,17 +119,6 @@ let isTerminator = 1 in
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// a pattern) and the FPI instruction should have emission info (e.g. opcode
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// encoding and asm printing info).
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
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: I<o, F, outs, ins, asm, []> {}
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// FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
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: X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
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let FPForm = fp; let FPFormBits = FPForm.Value;
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let Pattern = pattern;
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}
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// Random Pseudo Instructions.
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def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
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[(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
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232
lib/Target/X86/X86InstrFormats.td
Normal file
232
lib/Target/X86/X86InstrFormats.td
Normal file
@ -0,0 +1,232 @@
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//===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<6> val> {
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bits<6> Value = val;
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}
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def Pseudo : Format<0>; def RawFrm : Format<1>;
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def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
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def MRMSrcMem : Format<6>;
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def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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def MRM6r : Format<22>; def MRM7r : Format<23>;
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def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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def MRM6m : Format<30>; def MRM7m : Format<31>;
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def MRMInitReg : Format<32>;
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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// machine code emitter.
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class ImmType<bits<3> val> {
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bits<3> Value = val;
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}
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def NoImm : ImmType<0>;
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def Imm8 : ImmType<1>;
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def Imm16 : ImmType<2>;
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def Imm32 : ImmType<3>;
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def Imm64 : ImmType<4>;
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// FPFormat - This specifies what form this FP instruction has. This is used by
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// the Floating-Point stackifier pass.
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class FPFormat<bits<3> val> {
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bits<3> Value = val;
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}
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def NotFP : FPFormat<0>;
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def ZeroArgFP : FPFormat<1>;
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def OneArgFP : FPFormat<2>;
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def OneArgFPRW : FPFormat<3>;
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def TwoArgFP : FPFormat<4>;
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def CompareFP : FPFormat<5>;
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def CondMovFP : FPFormat<6>;
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def SpecialFP : FPFormat<7>;
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// emitter that various prefix bytes are required.
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class OpSize { bit hasOpSizePrefix = 1; }
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class AdSize { bit hasAdSizePrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class TB { bits<4> Prefix = 1; }
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class REP { bits<4> Prefix = 2; }
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class D8 { bits<4> Prefix = 3; }
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class D9 { bits<4> Prefix = 4; }
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class DA { bits<4> Prefix = 5; }
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class DB { bits<4> Prefix = 6; }
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class DC { bits<4> Prefix = 7; }
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class DD { bits<4> Prefix = 8; }
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class DE { bits<4> Prefix = 9; }
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class DF { bits<4> Prefix = 10; }
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class XD { bits<4> Prefix = 11; }
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class XS { bits<4> Prefix = 12; }
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class T8 { bits<4> Prefix = 13; }
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class TA { bits<4> Prefix = 14; }
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr>
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: Instruction {
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let Namespace = "X86";
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bits<8> Opcode = opcod;
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Format Form = f;
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bits<6> FormBits = Form.Value;
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ImmType ImmT = i;
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bits<3> ImmTypeBits = ImmT.Value;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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string AsmString = AsmStr;
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//
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// Attributes specific to X86 instructions...
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//
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
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FPFormat FPForm; // What flavor of FP instruction is this?
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bits<3> FPFormBits = 0;
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}
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class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
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: X86Inst<o, f, NoImm, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
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: X86Inst<o, f, Imm8 , outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
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: X86Inst<o, f, Imm16, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
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: X86Inst<o, f, Imm32, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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// FPStack Instruction Templates:
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
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: I<o, F, outs, ins, asm, []> {}
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// FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
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: X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
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let FPForm = fp; let FPFormBits = FPForm.Value;
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let Pattern = pattern;
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}
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// SSE1 Instruction Templates:
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//
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// SSI - SSE1 instructions with XS prefix.
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// PSI - SSE1 instructions with TB prefix.
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// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
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class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
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class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
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class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
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// SSE2 Instruction Templates:
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//
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// SDI - SSE2 instructions with XD prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
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class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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// SSE3 Instruction Templates:
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//
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// S3I - SSE3 instructions with TB and OpSize prefixes.
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// S3SI - SSE3 instructions with XS prefix.
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// S3DI - SSE3 instructions with XD prefix.
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class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>;
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class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>;
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class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
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// X86-64 Instruction templates...
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//
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class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, REX_W;
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class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, REX_W;
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class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii32<o, F, outs, ins, asm, pattern>, REX_W;
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class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: SSI<o, F, outs, ins, asm, pattern>, REX_W;
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class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: SDI<o, F, outs, ins, asm, pattern>, REX_W;
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class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: PDI<o, F, outs, ins, asm, pattern>, REX_W;
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// MMX Instruction templates
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//
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// MMXI - MMX instructions with TB prefix.
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// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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// MMXID - MMX instructions with XD prefix.
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// MMXIS - MMX instructions with XS prefix.
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class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
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class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
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class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
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class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
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@ -152,29 +152,6 @@ def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
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def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
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[add, mul, shl, or, frameindex], []>;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<6> val> {
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bits<6> Value = val;
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}
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def Pseudo : Format<0>; def RawFrm : Format<1>;
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def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
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def MRMSrcMem : Format<6>;
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def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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def MRM6r : Format<22>; def MRM7r : Format<23>;
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def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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def MRM6m : Format<30>; def MRM7m : Format<31>;
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def MRMInitReg : Format<32>;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Predicate Definitions.
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def HasMMX : Predicate<"Subtarget->hasMMX()">;
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@ -190,84 +167,10 @@ def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
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def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
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//===----------------------------------------------------------------------===//
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// X86 specific pattern fragments.
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// X86 Instruction Format Definitions.
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//
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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// machine code emitter.
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class ImmType<bits<3> val> {
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bits<3> Value = val;
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}
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def NoImm : ImmType<0>;
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def Imm8 : ImmType<1>;
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def Imm16 : ImmType<2>;
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def Imm32 : ImmType<3>;
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def Imm64 : ImmType<4>;
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// FPFormat - This specifies what form this FP instruction has. This is used by
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// the Floating-Point stackifier pass.
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class FPFormat<bits<3> val> {
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bits<3> Value = val;
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}
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def NotFP : FPFormat<0>;
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def ZeroArgFP : FPFormat<1>;
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def OneArgFP : FPFormat<2>;
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def OneArgFPRW : FPFormat<3>;
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def TwoArgFP : FPFormat<4>;
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def CompareFP : FPFormat<5>;
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def CondMovFP : FPFormat<6>;
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def SpecialFP : FPFormat<7>;
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr>
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: Instruction {
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let Namespace = "X86";
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bits<8> Opcode = opcod;
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Format Form = f;
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bits<6> FormBits = Form.Value;
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ImmType ImmT = i;
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bits<3> ImmTypeBits = ImmT.Value;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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string AsmString = AsmStr;
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//
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// Attributes specific to X86 instructions...
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//
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
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FPFormat FPForm; // What flavor of FP instruction is this?
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bits<3> FPFormBits = 0;
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}
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// emitter that various prefix bytes are required.
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class OpSize { bit hasOpSizePrefix = 1; }
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class AdSize { bit hasAdSizePrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class TB { bits<4> Prefix = 1; }
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class REP { bits<4> Prefix = 2; }
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class D8 { bits<4> Prefix = 3; }
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class D9 { bits<4> Prefix = 4; }
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class DA { bits<4> Prefix = 5; }
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class DB { bits<4> Prefix = 6; }
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class DC { bits<4> Prefix = 7; }
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class DD { bits<4> Prefix = 8; }
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class DE { bits<4> Prefix = 9; }
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class DF { bits<4> Prefix = 10; }
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class XD { bits<4> Prefix = 11; }
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class XS { bits<4> Prefix = 12; }
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class T8 { bits<4> Prefix = 13; }
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class TA { bits<4> Prefix = 14; }
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include "X86InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Pattern fragments...
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@ -333,31 +236,6 @@ def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
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def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
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def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// Instruction templates...
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//
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class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
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: X86Inst<o, f, NoImm, outs, ins, asm> {
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let Pattern = pattern;
|
||||
let CodeSize = 3;
|
||||
}
|
||||
class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: X86Inst<o, f, Imm8 , outs, ins, asm> {
|
||||
let Pattern = pattern;
|
||||
let CodeSize = 3;
|
||||
}
|
||||
class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: X86Inst<o, f, Imm16, outs, ins, asm> {
|
||||
let Pattern = pattern;
|
||||
let CodeSize = 3;
|
||||
}
|
||||
class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: X86Inst<o, f, Imm32, outs, ins, asm> {
|
||||
let Pattern = pattern;
|
||||
let CodeSize = 3;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction list...
|
||||
//
|
||||
@ -2653,6 +2531,12 @@ def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
|
||||
|
||||
include "X86InstrFPStack.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86-64 Support
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "X86InstrX86-64.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2664,9 +2548,3 @@ include "X86InstrMMX.td"
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "X86InstrSSE.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86-64 Support
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "X86InstrX86-64.td"
|
||||
|
||||
@ -13,29 +13,6 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction templates
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// MMXI - MMX instructions with TB prefix.
|
||||
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
|
||||
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
|
||||
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
|
||||
// MMXID - MMX instructions with XD prefix.
|
||||
// MMXIS - MMX instructions with XS prefix.
|
||||
class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
|
||||
class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
|
||||
class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
|
||||
class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
|
||||
class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
|
||||
class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
|
||||
|
||||
// Some 'special' instructions
|
||||
def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
|
||||
"#IMPLICIT_DEF $dst",
|
||||
|
||||
@ -277,20 +277,6 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
|
||||
// SSE1 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// SSE1 Instruction Templates:
|
||||
//
|
||||
// SSI - SSE1 instructions with XS prefix.
|
||||
// PSI - SSE1 instructions with TB prefix.
|
||||
// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
|
||||
|
||||
class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
|
||||
class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
|
||||
class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
|
||||
|
||||
// Move Instructions
|
||||
def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
|
||||
"movss {$src, $dst|$dst, $src}", []>;
|
||||
@ -947,20 +933,6 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
|
||||
// SSE2 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// SSE2 Instruction Templates:
|
||||
//
|
||||
// SDI - SSE2 instructions with XD prefix.
|
||||
// PDI - SSE2 instructions with TB and OpSize prefixes.
|
||||
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
|
||||
|
||||
class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
|
||||
class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
|
||||
class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
|
||||
|
||||
// Move Instructions
|
||||
def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
|
||||
"movsd {$src, $dst|$dst, $src}", []>;
|
||||
@ -2180,19 +2152,6 @@ def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
||||
// SSE3 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// SSE3 Instruction Templates:
|
||||
//
|
||||
// S3I - SSE3 instructions with TB and OpSize prefixes.
|
||||
// S3SI - SSE3 instructions with XS prefix.
|
||||
// S3DI - SSE3 instructions with XD prefix.
|
||||
|
||||
class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>;
|
||||
class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>;
|
||||
class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
|
||||
|
||||
// Move Instructions
|
||||
def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"movshdup {$src, $dst|$dst, $src}",
|
||||
@ -2655,3 +2614,11 @@ def : Pat<(store (v8i16 VR128:$src), addr:$dst),
|
||||
(MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(store (v16i8 VR128:$src), addr:$dst),
|
||||
(MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
|
||||
// (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
|
||||
def : Pat<(vector_extract
|
||||
(bc_v4i32 (v4f32 (scalar_to_vector (loadf32 addr:$src)))), (iPTR 0)),
|
||||
(MOV32rm addr:$src)>;
|
||||
def : Pat<(vector_extract
|
||||
(bc_v2i64 (v2f64 (scalar_to_vector (loadf64 addr:$src)))), (iPTR 0)),
|
||||
(MOV64rm addr:$src)>;
|
||||
|
||||
@ -39,36 +39,6 @@ def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
|
||||
[add, mul, shl, or, frameindex, X86Wrapper],
|
||||
[]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction templates...
|
||||
//
|
||||
|
||||
class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, REX_W;
|
||||
class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, REX_W;
|
||||
class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: Ii32<o, F, outs, ins, asm, pattern>, REX_W;
|
||||
|
||||
class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
|
||||
let Pattern = pattern;
|
||||
let CodeSize = 3;
|
||||
}
|
||||
|
||||
class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: SSI<o, F, outs, ins, asm, pattern>, REX_W;
|
||||
class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: SDI<o, F, outs, ins, asm, pattern>, REX_W;
|
||||
class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: PDI<o, F, outs, ins, asm, pattern>, REX_W;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pattern fragments...
|
||||
//
|
||||
|
||||
16
test/CodeGen/X86/2007-07-31-VInsertBug.ll
Normal file
16
test/CodeGen/X86/2007-07-31-VInsertBug.ll
Normal file
@ -0,0 +1,16 @@
|
||||
; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | %prcontext {pinsrw \$2} 1 | grep "movl \$1"
|
||||
; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | not grep movss
|
||||
|
||||
@G = global <4 x float> zeroinitializer
|
||||
|
||||
define void @test(i32 *%P1, i32* %P2, float *%FP) {
|
||||
%T = load float* %FP
|
||||
store i32 0, i32* %P1
|
||||
|
||||
%U = load <4 x float>* @G
|
||||
store i32 1, i32* %P1
|
||||
%V = insertelement <4 x float> %U, float %T, i32 1
|
||||
store <4 x float> %V, <4 x float>* @G
|
||||
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user