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Eliminate duplicate target pointer. Also add a few assertions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4128 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -26,7 +26,7 @@ using std::cerr;
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using std::vector;
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UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
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: MachineRegInfo(tgt), NumOfIntArgRegs(6),
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NumOfFloatArgRegs(32), InvalidRegNum(1000) {
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MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
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@ -564,7 +564,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
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LiveRangeInfo& LRI) const {
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assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
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assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
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CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
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@ -750,7 +750,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
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PhyRegAlloc &PRA,
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const BasicBlock *BB) const {
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assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
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assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
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CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
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@ -955,7 +955,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
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void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
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LiveRangeInfo &LRI) const {
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assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
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assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
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suggestReg4RetAddr(RetMI, LRI);
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@ -993,7 +993,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
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LiveRangeInfo &LRI,
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AddedInstrns *RetAI) const {
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assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
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assert((target.getInstrInfo()).isReturn( RetMI->getOpCode()));
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// if there is an implicit ref, that has to be the ret value
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if(RetMI->getNumImplicitRefs() > 0) {
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@ -1149,6 +1149,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
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MachineInstr * MI = NULL;
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switch( RegType ) {
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case IntRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
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MI = new MachineInstr(STX, 3);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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@ -1158,6 +1159,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
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break;
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case FPSingleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
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MI = new MachineInstr(ST, 3);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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@ -1167,6 +1169,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
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break;
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case FPDoubleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
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MI = new MachineInstr(STD, 3);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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@ -1188,6 +1191,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
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case FloatCCRegType:
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assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
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assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
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MI = new MachineInstr(STXFSR, 3);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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@ -1218,6 +1222,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
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MachineInstr * MI = NULL;
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switch (RegType) {
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case IntRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
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MI = new MachineInstr(LDX, 3);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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@ -1227,6 +1232,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
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break;
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case FPSingleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
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MI = new MachineInstr(LD, 3);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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@ -1236,6 +1242,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
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break;
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case FPDoubleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
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MI = new MachineInstr(LDD, 3);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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@ -1257,6 +1264,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
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case FloatCCRegType:
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assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
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assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
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MI = new MachineInstr(LDXFSR, 3);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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@ -1342,7 +1350,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
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const BasicBlock *BB,
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PhyRegAlloc &PRA) const
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{
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assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
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assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
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// has set to record which registers were saved/restored
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//
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