diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 88e2fa15ee7..9b7f6fc6aee 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2091,7 +2091,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
     // tailcall must happen after callee-saved registers are poped.
     // FIXME: Give it a special register class that contains caller-saved
     // register instead?
-    unsigned TCReg = Is64Bit ? X86::R11 : X86::ECX;
+    unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
     Chain = DAG.getCopyToReg(Chain,  dl,
                              DAG.getRegister(TCReg, getPointerTy()),
                              Callee,InFlag);
@@ -2145,7 +2145,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
     }
 
     assert(((Callee.getOpcode() == ISD::Register &&
-               (cast<RegisterSDNode>(Callee)->getReg() == X86::ECX ||
+               (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
                 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
               Callee.getOpcode() == ISD::TargetExternalSymbol ||
               Callee.getOpcode() == ISD::TargetGlobalAddress) &&
diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll
index 8bfae1bb8de..3841f518976 100644
--- a/test/CodeGen/X86/tailcallfp2.ll
+++ b/test/CodeGen/X86/tailcallfp2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%ecx}
+; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax}
 
 declare i32 @putchar(i32)