From c6a19dd7fbfce7668920daff2845abb2dd73a134 Mon Sep 17 00:00:00 2001
From: Andrew Trick <atrick@apple.com>
Date: Wed, 21 Mar 2012 04:12:19 +0000
Subject: [PATCH] misched: beginning to add unit tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153163 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/Generic/misched.ll | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 test/CodeGen/Generic/misched.ll

diff --git a/test/CodeGen/Generic/misched.ll b/test/CodeGen/Generic/misched.ll
new file mode 100644
index 00000000000..6ab1dd24a3c
--- /dev/null
+++ b/test/CodeGen/Generic/misched.ll
@@ -0,0 +1,20 @@
+; RUN: llc -enable-misched -misched=shuffle -misched-bottomup < %s
+; XFAIL: *
+;
+; Interesting MachineScheduler cases.
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
+
+; From oggenc.
+; After coalescing, we have a dead superreg (RAX) definition.
+define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
+entry:
+  br i1 undef, label %for.cond.preheader, label %if.end
+
+for.cond.preheader:                               ; preds = %entry
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 128, i32 4, i1 false) nounwind
+  unreachable
+
+if.end:                                           ; preds = %entry
+  ret void
+}