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DAG post-process for Hexagon MI scheduler

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This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sergei Larin 2012-09-14 15:07:59 +00:00
parent c5252da873
commit c6a6660c62
2 changed files with 34 additions and 0 deletions
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27
lib/Target/Hexagon/HexagonMachineScheduler.cpp
View File

@ -20,6 +20,22 @@
using namespace llvm;
/// Platform specific modifications to DAG.
void VLIWMachineScheduler::postprocessDAG() {
SUnit* LastSequentialCall = NULL;
// Currently we only catch the situation when compare gets scheduled
// before preceding call.
for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
// Remember the call.
if (SUnits[su].getInstr()->isCall())
LastSequentialCall = &(SUnits[su]);
// Look for a compare that defines a predicate.
else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
SUnits[su].addPred(SDep(LastSequentialCall, SDep::Order, 0, /*Reg=*/0,
false));
}
}
/// Check if scheduling of this SU is possible
/// in the current packet.
/// It is _not_ precise (statefull), it is more like
@ -67,6 +83,13 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
/// Keep track of available resources.
bool VLIWResourceModel::reserveResources(SUnit *SU) {
bool startNewCycle = false;
// Artificially reset state.
if (!SU) {
ResourcesModel->clearResources();
Packet.clear();
TotalPackets++;
return false;
}
// If this SU does not fit in the packet
// start a new one.
if (!isResourceAvailable(SU)) {
@ -128,6 +151,9 @@ void VLIWMachineScheduler::schedule() {
buildDAGWithRegPressure();
// Postprocess the DAG to add platform specific artificial dependencies.
postprocessDAG();
// To view Height/Depth correctly, they should be accessed at least once.
DEBUG(unsigned maxH = 0;
for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
@ -354,6 +380,7 @@ SUnit *ConvergingVLIWScheduler::SchedBoundary::pickOnlyChoice() {
for (unsigned i = 0; Available.empty(); ++i) {
assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
"permanent hazard"); (void)i;
ResourceModel->reserveResources(0);
bumpCycle();
releasePending();
}

7
lib/Target/Hexagon/HexagonMachineScheduler.h
View File

@ -114,6 +114,8 @@ public:
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
virtual void schedule();
/// Perform platform specific DAG postprocessing.
void postprocessDAG();
};
/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
@ -222,6 +224,11 @@ public:
virtual void releaseBottomNode(SUnit *SU);
unsigned ReportPackets() {
return Top.ResourceModel->getTotalPackets() +
Bot.ResourceModel->getTotalPackets();
}
protected:
SUnit *pickNodeBidrectional(bool &IsTopNode);